V
Volker Kriszeit
Guest
Hi folks,
currently I'm developing a small 2-stage RISC processor. For that, I use
the ALDEC Active-HDL 10.5 simulator to have a look into the design for
debugging purposes. That's working fine, but I want to switch to a VHDL
testbench to automate the validations.
Is there any possibility in the main testbench to get access to signals
deep down in my design when I want to ASSERT some signal? I have asked
google but it always responds with some somewhat trivial syntax
definitions for the ASSERT statement.
Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?
Or am I bound to the top level signals and can't look into the design
using ASSERT? What would be the proper way to do this in a testbench? I
prefer to not alter the design to pass internal signals to the top level
to be able to check them.
TIA
currently I'm developing a small 2-stage RISC processor. For that, I use
the ALDEC Active-HDL 10.5 simulator to have a look into the design for
debugging purposes. That's working fine, but I want to switch to a VHDL
testbench to automate the validations.
Is there any possibility in the main testbench to get access to signals
deep down in my design when I want to ASSERT some signal? I have asked
google but it always responds with some somewhat trivial syntax
definitions for the ASSERT statement.
Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?
Or am I bound to the top level signals and can't look into the design
using ASSERT? What would be the proper way to do this in a testbench? I
prefer to not alter the design to pass internal signals to the top level
to be able to check them.
TIA