Can we log internal signals from a testbench in VHDL?

You can build your own.

....
use STD.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;
....
write(my_line, string'("presState "));
write(my_line, string'(STATETYPE'image(presState)));
write(my_line, string'(" at "));
write(my_line, now);
writeline(output, my_line);

For more details see
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_print_debug_tip.html

To print instance path:
1.if(newByte = '1') then

2. write (my_line, string'("path "));

3. write (my_line, clk'path_name);--short
.....
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_path_name_print.html




On Friday, November 9, 2012 at 6:08:07 AM UTC+2, py wrote:

Hi,

At the end of a test, I would like to collect some stat in the following manner:

assert false report "Max counter is " & str(counter_value) severity note

This syntax won't work if counter_value is embedded inside DUT and is not a IO port. Is there any way to "peak" inside the inner layer? I heard that for verilog, it is possible to reference internal signal like outer_layer.inner_layer.signal_name


Thanks