P
Przemyslaw Bazarnik
Guest
I have problem related to related to Synopsys synthesis of
asynchronous load fflop and library design (Artisan)
I wonder if anyone got satisfying solution to this issue.
We follow asynchronous reset assertion and synchronous deassertion
methodology and use the async data for initializing power on register
values. We have couple of registers with asynchronous load for
strapping and synchronous load for normal operation (register load).
In several cases async data comes from input or bidir io pad
which has also other (normal mode) function.
Async load example:
module async_load (clk, rst, adata, sdata, sload, q);
input clk, rst, adata, sdata, sload;
output q;
reg q;
always @ (posedge clk or posedge rst)
if (rst)
q <= adata;
else if (sload)
q <= sdata;
endmodule
The above gets synthesized as fflop with async set and reset inputs
and a few gates.
1. What we want is:
S = adata AND rst
R = (NOT adata) AND rst
2. What we get with Artisan lib is:
S = rst
R = (NOT adata) AND rst
Due to Artisan fflops allowing assertion of both set and reset (reset
dominates) the logic generating async set gets optimized (AND gate is
removed). This causes problems when timing over rst -> S path is
longer than rst -> R path (possible with buffering and routing
delays): in case of adata=0 R gets deasserted first and the S last.
The effect is that FF is incorrectly set (should be reset since adata
is 0)
Few ways to solve the issue:
1. Clever constraints to make Synopsys notice timing problem.
Con:
Timing driven layout tool not likely to get it right.
Elaborate constraints on input used in normal operation for different
function whatsoever (may have different clock domain)
2. Modify library to disallow simultaneous set and reset assertion.
Con: Dirty.
Not possible for libraries delivered in binary format (db)
3. Abandon whole async load idea.
Con: async load is simple and efficient. Any replacement logic
is bound to be more complex or need to use rst as sync input.
Thanks,
Przemek
asynchronous load fflop and library design (Artisan)
I wonder if anyone got satisfying solution to this issue.
We follow asynchronous reset assertion and synchronous deassertion
methodology and use the async data for initializing power on register
values. We have couple of registers with asynchronous load for
strapping and synchronous load for normal operation (register load).
In several cases async data comes from input or bidir io pad
which has also other (normal mode) function.
Async load example:
module async_load (clk, rst, adata, sdata, sload, q);
input clk, rst, adata, sdata, sload;
output q;
reg q;
always @ (posedge clk or posedge rst)
if (rst)
q <= adata;
else if (sload)
q <= sdata;
endmodule
The above gets synthesized as fflop with async set and reset inputs
and a few gates.
1. What we want is:
S = adata AND rst
R = (NOT adata) AND rst
2. What we get with Artisan lib is:
S = rst
R = (NOT adata) AND rst
Due to Artisan fflops allowing assertion of both set and reset (reset
dominates) the logic generating async set gets optimized (AND gate is
removed). This causes problems when timing over rst -> S path is
longer than rst -> R path (possible with buffering and routing
delays): in case of adata=0 R gets deasserted first and the S last.
The effect is that FF is incorrectly set (should be reset since adata
is 0)
Few ways to solve the issue:
1. Clever constraints to make Synopsys notice timing problem.
Con:
Timing driven layout tool not likely to get it right.
Elaborate constraints on input used in normal operation for different
function whatsoever (may have different clock domain)
2. Modify library to disallow simultaneous set and reset assertion.
Con: Dirty.
Not possible for libraries delivered in binary format (db)
3. Abandon whole async load idea.
Con: async load is simple and efficient. Any replacement logic
is bound to be more complex or need to use rst as sync input.
Thanks,
Przemek