Assign same signal in one block - Verilog

Guest
Hi,

I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look:

parameter VALID_BIT = 0;
[...]
if(data_in_cfg[VALID_BIT] == 0) begin
data_out_cfg <= {DATA_WIDTH{1'b1}};
data_out_cfg[VALID_BIT] <= 1'b0;
end else begin
data_out_cfg <= (data_in_cfg >> BIT_NUMBERS);
data_out_cfg[VALID_BIT] <= 1'b1;
end
 
george.isachi@gmail.com wrote:
Hi,

I want to make an assignment to a output signal in the same block but I need to keep some information and for that I need to do a double assignment in the same block. Can you please take a look:

parameter VALID_BIT = 0;
[...]
if(data_in_cfg[VALID_BIT] == 0) begin
data_out_cfg <= {DATA_WIDTH{1'b1}};
data_out_cfg[VALID_BIT] <= 1'b0;
end else begin
data_out_cfg <= (data_in_cfg >> BIT_NUMBERS);
data_out_cfg[VALID_BIT] <= 1'b1;
end

You do realize this is a VHDL newsgroup - setting follow-up to
comp.lang.verilog

It's not clear what your question is. Are you talking about
first assigning all bits of data_out_cfg and then assigning
only the VALID bit? That's perfectly acceptable and the final
assigned value would be the same as if you only assigned bits
other than the VALID bit in the first assignment (no "double"
assignment). i.e. the last assignment "wins" when you make
more than one.

--
Gabor
 

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