S
smu
Guest
Hello,
I search the good syntax for do anything like
architecture ... of ... is
signal s : array(0 to 28) of std_logic_vector(15 downto 0);
begin
process (clk)
begin
s( 1)(15 downto 0) <= s( 0)(15 downto 0);
s( 2)(15 downto 0) <= s( 1)(15 downto 0);
....
end;
end;
That is the good way to code the signal declaration ?
In the final version, I use GENERATE to replace the current process coding.
Thank you in advance
smu
I search the good syntax for do anything like
architecture ... of ... is
signal s : array(0 to 28) of std_logic_vector(15 downto 0);
begin
process (clk)
begin
s( 1)(15 downto 0) <= s( 0)(15 downto 0);
s( 2)(15 downto 0) <= s( 1)(15 downto 0);
....
end;
end;
That is the good way to code the signal declaration ?
In the final version, I use GENERATE to replace the current process coding.
Thank you in advance
smu