W
walala
Guest
Dear all,
I want to ask a question about FILE I/O using VHDL during
simulation. My project requires a close collaboration between matlab
and VHDL simulation. I need to import data generated from matlab
into VHDL program and then execute and get results exported into
matlab for further analysis.
Is there a way to open/save file for exchanging data in VHDL?
Thanks a lot,
-Walala
I want to ask a question about FILE I/O using VHDL during
simulation. My project requires a close collaboration between matlab
and VHDL simulation. I need to import data generated from matlab
into VHDL program and then execute and get results exported into
matlab for further analysis.
Is there a way to open/save file for exchanging data in VHDL?
Thanks a lot,
-Walala