another newbie question about vhdl

[Max]

the following source has a strange behaviour
-----------8<-----------------
entity main is
Port ( clk : in std_logic;
cnt : inout std_logic_vector(2 downto 0);
o: out std_logic;
en : in std_logic);
end main;

architecture Behavioral of main is

begin

process (clk, en)
begin
if en = '0' then
cnt <= (others => '0');
o <= '0';
elsif rising_edge(clk) then
cnt <= cnt + 1;
if cnt = 1 then
o <= '1';
end if;
end if;
end process;

end Behavioral;
------8<---------------

I'm expecting that o goes high at first rising edge of clk, after en
goes high.
Instead this happens after another clock cycle.
Debugging this code I found that cnt is not updated immediatly, is it
right?

thanks

 

[Egbert Molenkamp]

elsif rising_edge(clk) then
cnt <= cnt + 1;

Instead this happens after another clock cycle.
Debugging this code I found that cnt is not updated immediatly, is it
right?

Remember:
- signals are NEVER updated immediatly
- variables are updated immediatly

Signals are used to communicate between processes. To be order independent
all processes use the SAME signal value.
Therefore the update of signals is postponed (as you have noticed during
debugging).
Read a good book that explains this in more detail. Or use google (e.g.
update signals VHDL) to find additional stuff.

Egbert Molenkamp

 

[Ralf Hildebrandt]

Hi Max!

process (clk, en)
begin
if en = '0' then
cnt <= (others => '0');
o <= '0';
elsif rising_edge(clk) then
cnt <= cnt + 1;
if cnt = 1 then
o <= '1';
end if;
end if;
end process;

end Behavioral;
------8<---------------

I'm expecting that o goes high at first rising edge of clk, after en
goes high.
Instead this happens after another clock cycle.

This is o.k..

Let's simulate it:

* "en" changes (from 0 to 1) -> the process is executed, no if-branch
is entered

* clk changes -> if it was a rising_edge, the corresponding if-branch
is chosen
cnt<=cnt+1; is computed, but (!) cnt is updated in the next
delta-cycle
if cnt=1 then <- cnt has the old (!) value, because it is updated in
the next delta-cycle, not immediately (like a variable)


Lets have a look at the circuit:
cnt and o are flipflops. Some wires are connected to the inputs.
Flipflops load the value at the inputs during the rising / falling edge
of the clock-signal.
When the rising_edge(clk) comes, cnt is loaded with the new value
(cnt+1). The new value is visible at the ouput of fliflop cnt
(immediately) and then _ribbles_ through a half-adder. The means, cnt+1
is "computed" _later_ than flipflop cnt is updated.
-> At the moment cnt is updated at the rising_edge(clk), the test, if
cnt=1, cannot test the new value.


----
--------|+1|----<---
| ---- |
-->--------- |
|cnt|-------
clk----------


Summary: The addition "+1" takes some time.


Ralf