Altera synthesis of registered signals ???

V

Vazquez

Guest
Dear Sir or Madame,

I have the following problem:

In a clocked process I made the following registered signal
assignments:

------------------------------------------------------------
------------------------------------------------------------
entity xy is
port( addr_to_send : in std_logic_vector(6 downto 0);
ep_to_send : in std_logic_vector(3 downto 0);
addr_rec : in std_logic_vector(6 downto 0);
ep_rec : in std_logic_vector(3 downto 0);
direction_to_send : in std_logic;
cam_ram_entry_valid : in std_logic;
...
);
end xy;

architecture ...

process(write_clock)
begin
if rising_edge(write_clock) then

l_data_addr_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(2
downto 0) );

l_data_addr_rec <= ( addr_rec(6 downto 0) & ep_rec(2 downto
0) );

l_data_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(3
downto 0) & direction_to_send & cam_ram_entry_valid);

end if;
end process;

--------------------------------------------------------------
--------------------------------------------------------------

When I open the NodeFinder in the AlteraQuartusII software (after
Synthesis)I
see that
- l_data_addr_to_send are registered nodes : OK

- only l_data_rec[0], l_data_rec[4] are registered nodes
the other bits of l_data_rec are not shown at all ???

- only l_data_to_send[0], l_data_to_send[1], l_data_to_send[5] are
registered nodes
the other bits of l_data_to_send are not shown at all ???

So my question: Why did the synthesis tool not recognize all bits
to be registered ?

Thank you very much.

Kind regards

Andrés Vázquez
 
You really need a reset assignment on this for starters....

"Vazquez" <andres.vazquez@gmx.de> wrote in message
news:eee19a7a.0311170507.4495f94d@posting.google.com...
Dear Sir or Madame,

I have the following problem:

In a clocked process I made the following registered signal
assignments:

------------------------------------------------------------
------------------------------------------------------------
entity xy is
port( addr_to_send : in std_logic_vector(6 downto 0);
ep_to_send : in std_logic_vector(3 downto 0);
addr_rec : in std_logic_vector(6 downto 0);
ep_rec : in std_logic_vector(3 downto 0);
direction_to_send : in std_logic;
cam_ram_entry_valid : in std_logic;
...
);
end xy;

architecture ...

process(write_clock)
begin
if rising_edge(write_clock) then

l_data_addr_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(2
downto 0) );

l_data_addr_rec <= ( addr_rec(6 downto 0) & ep_rec(2 downto
0) );

l_data_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(3
downto 0) & direction_to_send & cam_ram_entry_valid);

end if;
end process;

--------------------------------------------------------------
--------------------------------------------------------------

When I open the NodeFinder in the AlteraQuartusII software (after
Synthesis)I
see that
- l_data_addr_to_send are registered nodes : OK

- only l_data_rec[0], l_data_rec[4] are registered nodes
the other bits of l_data_rec are not shown at all ???

- only l_data_to_send[0], l_data_to_send[1], l_data_to_send[5] are
registered nodes
the other bits of l_data_to_send are not shown at all ???

So my question: Why did the synthesis tool not recognize all bits
to be registered ?

Thank you very much.

Kind regards

Andrés Vázquez
Click to expand...
 
andres.vazquez@gmx.de (Vazquez) wrote in message news:<eee19a7a.0311170507.4495f94d@posting.google.com>...
Dear Sir or Madame,

I have the following problem:

In a clocked process I made the following registered signal
assignments:

------------------------------------------------------------
------------------------------------------------------------
entity xy is
port( addr_to_send : in std_logic_vector(6 downto 0);
ep_to_send : in std_logic_vector(3 downto 0);
addr_rec : in std_logic_vector(6 downto 0);
ep_rec : in std_logic_vector(3 downto 0);
direction_to_send : in std_logic;
cam_ram_entry_valid : in std_logic;
...
);
end xy;

architecture ...

process(write_clock)
begin
if rising_edge(write_clock) then

l_data_addr_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(2
downto 0) );

l_data_addr_rec <= ( addr_rec(6 downto 0) & ep_rec(2 downto
0) );

l_data_to_send <= ( addr_to_send(6 downto 0) & ep_to_send(3
downto 0) & direction_to_send & cam_ram_entry_valid);

end if;
end process;

--------------------------------------------------------------
--------------------------------------------------------------

When I open the NodeFinder in the AlteraQuartusII software (after
Synthesis)I
see that
- l_data_addr_to_send are registered nodes : OK

- only l_data_rec[0], l_data_rec[4] are registered nodes
the other bits of l_data_rec are not shown at all ???

- only l_data_to_send[0], l_data_to_send[1], l_data_to_send[5] are
registered nodes
the other bits of l_data_to_send are not shown at all ???

So my question: Why did the synthesis tool not recognize all bits
to be registered ?

Thank you very much.

Kind regards

Andrés Vázquez
Click to expand...
Hi Andrés,

The Quartus software is merging duplicate registers in the code
without altering the functionality of your design. Specifically,
l_data_addr_to_send and l_data_to_send are driven by many of the same
inputs; hence, it shares the registers implementing these signals. If
you want to keep all register bits, even duplicates, then
1.Use the Preserve Attribute on the registered signals, OR
2. Turn "Remove Duplicate Registers" off in the
Assignments->Settings->Default Logic Option Settings.

- Subroto Datta
Altera Corp
 
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