AHDL vs. Veriloga

[Kuan Zhou]

Hi,
I am making some codes for mixed-signal blocks.However,
I am facing a choice which language to use in Cadence.
Some people told me Veriloga is better than AHDL.Which is used
more in Industry?
I want to replace some blocks by codes, then my simulation
can run faster and the logic can be easily verified.


Thank you very much!


sincerely
-------------
Kuan Zhou
ECSE department

 

[Erik Wanta]

Kuan:
By ahdl, I assume you mean spectreHDL. Given the choice, I would
definitely go with veriloga as it is an IEEE standard.

Cadence supplies some sample libraries with veriloga code. They are
as follows:
$CDSHOME/tools/dfII/samples/artist/aExamples
$CDSHOME/tools/dfII/samples/artist/ahdlLib
$CDSHOME/tools/dfII/samples/artist/rfExamples
$CDSHOME/tools/dfII/samples/artist/rfLib
$CDSHOME/tools/dfII/samples/artist/pllLib

Look for the rfLib guide and behavioral models tutorial in the Cadence
documentation.

Cadence also has a tool called modelwriter that can create some simple
veriloga blocks.
---
Erik

Kuan Zhou <zhouk@rpi.edu> wrote in message news:<Pine.SOL.3.96.1030707173430.22029A-100000@vcmr-86.server.rpi.edu>...

Hi,
I am making some codes for mixed-signal blocks.However,
I am facing a choice which language to use in Cadence.
Some people told me Veriloga is better than AHDL.Which is used
more in Industry?
I want to replace some blocks by codes, then my simulation
can run faster and the logic can be easily verified.


Thank you very much!


sincerely
-------------
Kuan Zhou
ECSE department