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Aggregates on the Left Side of the Assignment...

R

Rick C

Guest
I can\'t figure out what is wrong with this left side aggregate. The right side is clearly defined. The left side is a std_logic combined with an unsigned which is not inappropriate as far as I can tell. Synplify and ActiveHDL both compile it ok, but ActiveHDL gives a run time error...

# RUNTIME: Fatal Error: RUNTIME_0046 VHDL_test.vhd (27): Incompatible ranges; left: (0 to 3), right: (0 downto 0).

signal count, nxt_cnt : unsigned(2 downto 0) := (others => \'0\');
signal Test_Out_v : std_logic := \'0\';
begin
Clk_gen: Clk <= not Clk after Clock_Half_Period;

(Carry_Out, nxt_cnt) <= RESIZE(count, nxt_cnt\'length + 1) - 1;

Pointing to the above line. It doesn\'t point to any part of the line.

I\'m stumped on this one.

--

Rick C.

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