VHDL Language

W
what is wrong with my VHDL code? I am so dissappointed...
Replies
3
Views
564
Ralf Hildebrandt
R
W
Silicore adopts open source business model for semiconductor
Replies
0
Views
280
Wade D. Peterson
W
M
again on state machine
Replies
4
Views
916
William Wallace
W
S
switching problem
Replies
5
Views
666
William Wallace
W
M
R: again on state machine
Replies
0
Views
265
Max
M
Y
string declaration
Replies
3
Views
665
Yann Sarrazin
Y
M
R: decoder
Replies
1
Views
541
Egbert Molenkamp
E
M
decoder
Replies
2
Views
597
Egbert Molenkamp
E
C
Design Flow: STA to Synthesis
Replies
1
Views
552
Brian Drummond
B
W
SOS! newbie question about synthesizable VHDL : synthesis ru
Replies
4
Views
665
Technology Consultant
T
W
Are all the signals read in the process should appear in the
Replies
3
Views
646
Allan Herriman
A
K
Manipulating with the T1, T0 and TX in a SAIF file.
Replies
0
Views
329
Kelvin Tsai @ Singapore
K
K
Synthesizing a design with RAM.
Replies
0
Views
279
Kelvin @ Singapore
K
V
predefined function/library
Replies
3
Views
590
Egbert Molenkamp
E
S
ModelSim and the Xilinix web pack unisim libraries
Replies
1
Views
555
Barry Brown
B
W
what are the possible reasons that successful pre-synthesis
Replies
4
Views
533
Ralf Hildebrandt
R
J
Question: inout signal assignment
Replies
1
Views
533
Renaud Pacalet
R
D
IP-Core CAn-controller
Replies
0
Views
301
Daniel Köthe
D
W
any VHDL books on low resource(throughput, area, power trade
Replies
0
Views
277
walala
W
M
(newbie) processo or not process?
Replies
7
Views
748
J. Bhasker
J
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