VHDL Language

W
Which is faster in ASIC: 2-input AND gate or a 2-input multi
Replies
12
Views
483
Neo
N
U
ROM
Replies
5
Views
330
m
M
?
problem with timing simulation
Replies
5
Views
405
Ralf Hildebrandt
R
?
Vector Slicing in assigments
Replies
5
Views
355
Zara
Z
E
Convert from std_logic_vector to real
Replies
2
Views
906
Hubble
H
D
Synthesizing high-density designs in Quartus
Replies
4
Views
345
Divyang M
D
B
I thought that this code compiled, now it does not?
Replies
1
Views
360
Ralf Hildebrandt
R
K
ModelSim control
Replies
6
Views
604
Kev P. (AKA Niv)
K
S
problem with modelsim
Replies
4
Views
482
sravan reddy
S
U
ModelSim Error
Replies
2
Views
522
Andy Peters
A
U
avoid latches
Replies
2
Views
376
Hubble
H
J
ANN: Zeus Version 3.95 Editor Released
Replies
0
Views
158
Jussi Jumppanen
J
B
Synchronising Reset APP Note
Replies
2
Views
345
Benjamin Todd
B
B
Dilemna w/ generic port of type array of slv
Replies
5
Views
387
combinational.logic $ soc
C
S
Problem in synthesizing function
Replies
1
Views
324
Ralf Hildebrandt
R
U
error in code?
Replies
5
Views
552
Ralf Hildebrandt
R
S
file lines reading
Replies
0
Views
194
srinukasam
S
T
Is it possible to define an alias of a type?
Replies
4
Views
379
Jonathan Bromley
J
W
Multiplexer Index
Replies
2
Views
389
woko
W
A
Synchronous Serial Port design
Replies
6
Views
475
Ralf Hildebrandt
R
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