VHDL Language

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LFSR doesn't generate random values during simulation
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9
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1K
Thomas Stanka
T
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create 400 clocks delay for a signal
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15
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2K
Thomas Stanka
T
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VHDL Verification components – The obvious solutio n to ef
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6
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1K
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User Defined Primitives
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1
Views
794
Gabor
G
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Same syntax for variable and signal update
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1
Views
799
Jim Lewis
J
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Entity instantiation in GHDL
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1
Views
944
Valentin Tihhomirov
V
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SciTE Editor for VHDL
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3
Views
899
rickman
R
F
test
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1
Views
890
rickman
R
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Gray Code
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15
Views
3K
rickman
R
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simple UART, tested with GHDL
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0
Views
419
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CPU 8051 translation from VHDL to verilog.
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0
Views
477
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C
[NEED HELP ARGENT!!]8-bit CPU system
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4
Views
1K
Maurice SAAB
M
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SRAM controller
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0
Views
394
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String list parser in VHDL...
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2
Views
1K
Allan Herriman
A
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Universal VHDL Verification Methodology (Free & Open source)
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0
Views
402
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newbio needs some help
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1
Views
1K
GaborSzakacs
G
M
entity component binding issue with configurations
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6
Views
2K
Allan Herriman
A
K
ADC_DAC_PGA_SPI_INTERFACE
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4
Views
2K
Michael Kellett
M
M
Help with multiplier code
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0
Views
427
Marvin L
M
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inter-dependent assignments in process
Replies
13
Views
2K
rickman
R
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