Xilinx ISE14: Problems with Sythesize

[Mathias Weierganz]

I am using Xilinx ISE14.7
I have a project for Spartan6 which I can compile without problems. Now
I try to compile it for a Virtex 5 and I run into problems already at
the synthesis level.

The first problem was easy to fix: The synthesis don't like the
concatenation operator "&" in the instantiation bloc.

But is there an easy solution for my second problem? The synthesis
don't want to see this construct:
databus_i => (others => '0'),
and give me this error message:
ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in
unconstrained array aggregate.

Let me say it again: I can compile the same project for Spartan-6
without any problems.


Any hints?

Thanks

Mathias

 

[Andy]

There are a lot of things that are non-compliant VHDL that are accepted by synthesis tools.

And a lot of compliant VHDL is not accepted by synthesis tools either.

Have you tried a simulator? They often have better error messages.

Is the port formal of an unconstrained type (i.e. takes its size from that of the associated actual)? If so, there is no pre-defined port-width from which "others" can be determined, and vise versa.

Andy

 

[GaborSzakacs]

Mathias Weierganz wrote:

I am using Xilinx ISE14.7
I have a project for Spartan6 which I can compile without problems. Now
I try to compile it for a Virtex 5 and I run into problems already at
the synthesis level.

The first problem was easy to fix: The synthesis don't like the
concatenation operator "&" in the instantiation bloc.

But is there an easy solution for my second problem? The synthesis
don't want to see this construct:
databus_i => (others => '0'),
and give me this error message:
ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in
unconstrained array aggregate.

Let me say it again: I can compile the same project for Spartan-6
without any problems.


Any hints?

Thanks

Mathias

Xilinx tools use a different front-end to synthesize 6-series and
newer FPGA's by default. If your code works with the new front-
end, you can try to use it on older parts. In the XST command
line add the option:

-use_new_parser yes

If you use the Navigator GUI, you can apply this option under
"Other XST Command Line Options" in the synthesis properties.

--
Gabor

 

[Brian Drummond]

On Wed, 26 Nov 2014 13:20:51 +0100, Mathias Weierganz wrote:

But is there an easy solution for my second problem? The synthesis don't
want to see this construct:
databus_i => (others => '0'),
and give me this error message:
ERROR:Xst:779 - "D:/Projekte/test_tdc/top.vhd" line 147: 'Others' is in
unconstrained array aggregate.

Easily solved by constraining the array aggregate:
databus_i => (databus_i'range => '0'),
making the code more portable

-- Brian

 

[Mathias Weierganz]

Am 26.11.2014 20:23, schrieb GaborSzakacs:

Xilinx tools use a different front-end to synthesize 6-series and
newer FPGA's by default. If your code works with the new front-
end, you can try to use it on older parts. In the XST command
line add the option:

-use_new_parser yes

If you use the Navigator GUI, you can apply this option under
"Other XST Command Line Options" in the synthesis properties.

This works fine for me. Many thanks for this hint.

Mathias