Xilinx ISE WebPack 5.2 & VHDL : wait synthesis

max · Aug 7, 2003

I tried this source code: entity main is 
&nbsp;&nbsp;&nbsp;&nbsp;Port ( clk , en : in std_logic; 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sout : out std_logic); 
end main; architecture Behavioral of main is 
begin 
&nbsp;&nbsp;process 
&nbsp;&nbsp;variable a : std_logic; 
&nbsp;&nbsp;begin 
&nbsp;&nbsp;&nbsp;&nbsp;sout <= '0'; 
&nbsp;&nbsp;&nbsp;&nbsp;a := '0'; 
&nbsp;&nbsp;&nbsp;&nbsp;wait until rising_edge(en); 
&nbsp;&nbsp;&nbsp;&nbsp;while en = '1' loop 
-- wait until rising_edge(clk); 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;wait until clk'event and clk = '1'; 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;a := not a; 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;sout <= a; 
&nbsp;&nbsp;&nbsp;&nbsp;end loop; 
&nbsp;&nbsp;end process; end Behavioral; and I obtain this error: Analyzing Entity <main> (Architecture <behavioral&gt

. 
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait statement in a procedure is not accepted. The question is: can I use wait or not? 
I found a lot of manual on the internet (eg. <a href="http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html)">http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html)</a>, and all of them sais that 'wait' is allowed in synthesis. thanks

Amontec Team, Laurent Gau · Aug 7, 2003

max wrote:

I tried this source code:

entity main is
Port ( clk , en : in std_logic;
sout : out std_logic);
end main;

architecture Behavioral of main is
begin
process
variable a : std_logic;
begin
sout <= '0';
a := '0';
wait until rising_edge(en);
while en = '1' loop
-- wait until rising_edge(clk);
wait until clk'event and clk = '1';
a := not a;
sout <= a;
end loop;
end process;

end Behavioral;

and I obtain this error:

Analyzing Entity <main> (Architecture <behavioral&gt.
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait
statement in a procedure is not accepted.

The question is: can I use wait or not?
I found a lot of manual on the internet (eg.
http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html), and all of
them sais that 'wait' is allowed in synthesis.

thanks

Your code is NOT a synthesable code.

Don't use 'wait' for synthesis code, but use 'wait' for your testbench
tester.

A synthesisable code will follow the rules:
- reset signal can be asynchro. or synchro.
- enable signal is ever synchro.
- if possible use only signal (don't use variable for synthesable code)

LOOK:

entity main is
Port ( clk , en : in std_ulogic;
sout : out std_ulogic);
end main;

architecture Behavioral of main is
signal a : std_ulogic;
begin
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
a <= not a;
sout <= a;
end if ;
end if;
end process;

end Behavioral;

PS: 'wait' and 'variable' are GREAT for simulation
try http://www.amontec.com/vhdl_part.shtml

Laurent Gauch
www.amontec.com

rickman · Aug 8, 2003

"Amontec Team, Laurent Gauch" wrote:

max wrote:
I tried this source code:

entity main is
Port ( clk , en : in std_logic;
sout : out std_logic);
end main;

architecture Behavioral of main is
begin
process
variable a : std_logic;
begin
sout <= '0';
a := '0';
wait until rising_edge(en);
while en = '1' loop
-- wait until rising_edge(clk);
wait until clk'event and clk = '1';
a := not a;
sout <= a;
end loop;
end process;

end Behavioral;

and I obtain this error:

Analyzing Entity <main> (Architecture <behavioral&gt.
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait
statement in a procedure is not accepted.

The question is: can I use wait or not?
I found a lot of manual on the internet (eg.
http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html), and all of
them sais that 'wait' is allowed in synthesis.

thanks

Your code is NOT a synthesable code.

Don't use 'wait' for synthesis code, but use 'wait' for your testbench
tester.

A synthesisable code will follow the rules:
- reset signal can be asynchro. or synchro.
- enable signal is ever synchro.
- if possible use only signal (don't use variable for synthesable code)

LOOK:

entity main is
Port ( clk , en : in std_ulogic;
sout : out std_ulogic);
end main;

architecture Behavioral of main is
signal a : std_ulogic;
begin
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
a <= not a;
sout <= a;
end if ;
end if;
end process;

end Behavioral;

PS: 'wait' and 'variable' are GREAT for simulation
try http://www.amontec.com/vhdl_part.shtml

Laurent Gauch
www.amontec.com

Yeah, I would second that opinion. Reading your code it looks like you
are treating VHDL as a software language rather than a hardware
language. To see what I mean, consider what you are trying to tell the
compiler to generate. If you can't figure out what the hardware should
look like, how can you expect the software to figure it out? I know
that I can't figure out what hardware you are trying to describe or what
could be built that would do what your software does. It clearly does
not describe a FF with logic feeding the D input and a clock enable
signal. There are too many waits for that.

Take a look at some synthesis templates for FFs and other hardware items
that you might want to generate. Don't think in terms of the language,
think in terms of the hardware you want to build. Then you should get
synthesizable code.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Xilinx ISE WebPack 5.2 & VHDL : wait synthesis

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