Wide bus

Suppose I have an n-input simple OR gate.

Result <= inp(0) or inp(1) or ...... or inp;

Q: how to write the above code for generic n?

 

[KJ]

On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com wrote:

Suppose I have an n-input simple OR gate.

Result <= inp(0) or inp(1) or ...... or inp;

Q: how to write the above code for generic n?

The function you want is called 'or_reduce' commonly found in the 'reduce_pkg' package.

Kevin Jennings

 

[rickman]

On 12/24/2015 3:49 PM, stchebel@gmail.com wrote:

Suppose I have an n-input simple OR gate.

Result <= inp(0) or inp(1) or ...... or inp;

Q: how to write the above code for generic n?

I believe there is an existing operator in VHDL 2008 to take the or of
each bit in a vector. If you can't find that use a for loop.

--

Rick

 

[Allan Herriman]

On Thu, 24 Dec 2015 16:17:45 -0800, KJ wrote:

On Thursday, December 24, 2015 at 3:49:53 PM UTC-5, stch...@gmail.com
wrote:
Suppose I have an n-input simple OR gate.

Result <= inp(0) or inp(1) or ...... or inp;

Q: how to write the above code for generic n?

The function you want is called 'or_reduce' commonly found in the
'reduce_pkg' package.

Kevin Jennings

or the ieee.std_logic_misc package. It's supported in all the tools I've
tried (even ones from Xilinx).

Regards,
Allan

 

[tuclogicguy]

<stchebel@gmail.com> wrote in message
news:1d70d046-2b56-494f-9b25-48338fed43a3@googlegroups.com...

Suppose I have an n-input simple OR gate.

Result <= inp(0) or inp(1) or ...... or inp;

Q: how to write the above code for generic n?

VHDL-2008 defines OR, AND and XOR reduction operators, analogous to
those in Verilog.
So, with VHDL-2008 you can just code
Result <= or inp;