why registered output?

[Alex]

Hi, all, I am a beginner in this field.
When I was reading and simulating others' designs, I found many of
them have their input and output registered. They use a Flip flop,
every rising edge of the clock, they have the outputed signal stored
in that flip flip, and then the output of the FF as the final output
of the design.

I am not quite understand why they want the registered signals, it
cause some delay since the final output will wait for the rising edge
of the clock. Is it for synchronization or something else? thanks.

 

[Pieter Hulshoff]

I am not quite understand why they want the registered signals, it
cause some delay since the final output will wait for the rising edge
of the clock. Is it for synchronization or something else? thanks.

It is done for timing purposes. As you know, all actions should be completed
before the next clock edge. In order to have as much timing margine as
possible, designers often clock in their inputs, and clock in their
outputs. That way the full clock cycle is available for routing purposes
for data transfer between two blocks.

Regards,

Pieter Hulshoff

 

[Chris Pruett]

It's often helpful when completing the physical design of a chip. Say
there are two blocks, A and B. A has unregistered outputs, B has
registered inputs. The timing budget from A to B would be something
like:

T1 := period(clk) - thold_A - toutput_A - tsetup_B

You can't do anything about thold_A or tsetup_B. toutput_A depends on
the logic in A between the flop and the output port.

Now say we replaced block A with a similar block C that has registered
oututs. The budget is:

T2 := period(clk) - thold_C - tsetup_B

thold_C =~ thold_A

Obviously, T2 is likely to be larger than T1. The more time you have
between blocks the further they can be from each other or perhaps your
clock speed will not be limited by block interconnect delays.

You're right though, it adds clock cycles to the path. Sometimes that
cannot be tolerated and then you really have to pay attention to the
logic in toutput_A and the floorplan.

CP


In article <65249cf1.0307260230.222495b0@posting.google.com>, Alex
<luwork@hotmail.com> wrote:

Hi, all, I am a beginner in this field.
When I was reading and simulating others' designs, I found many of
them have their input and output registered. They use a Flip flop,
every rising edge of the clock, they have the outputed signal stored
in that flip flip, and then the output of the FF as the final output
of the design.

I am not quite understand why they want the registered signals, it
cause some delay since the final output will wait for the rising edge
of the clock. Is it for synchronization or something else? thanks.

--
'When religion and politics ride in the same cart, the whirlwind follows.'