Why not DDR in FPGAs?

[itsme]

Hi all,
here is a quit simple, general question:
Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for
their FlipFlips?
+ This would reduce the power for the clock tree.
+ I could directly use the Data from an external DDR-DRAM

 

[Erik Widding]

"John_H" <johnhandwork@mail.com> wrote in message
news:afDMa.18$C_4.5194@news-west.eli.net...

The Xilinx CoolRunner also has the dual-edge option that they might refer
to
as an integrated clock doubler.

. I'd be interested to hear
if there is successful dual-edge synthesis for the existing devices with
dual-edge registers or DDR IOB registers.

I have not tried this with Synplicity yet. With XST the Coolriunner dual
edge flip flop is inferred with the following VHDL construct:

process(vclk)
begin
if (vclk'event) then
...
end if;
end process;

Which is exactly as one would expect. To get this inference to work, if
running XST with a script, the part type has to be set to XBR rather than
XC2C64 (as one would expect from the documentation). The flow engine sets
the part type correctly.


Regards,
Erik Widding.


---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

 

[Steven K. Knapp]

The Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGAs have DDR registers
as part of each I/O block.

For high-performance applications, you would want to use two outputs from
the Digital Clock Manager, one being the de-skewed, non-shifted clock output
and the de-skewed, 180 degrees phase-shifted clock output. This technique
minimizes any potential duty-cycle distortion and gives you most of the
entire half-period for your logic application.

You might take a look at the following web site as it contains both
application notes and sample code.
http://www.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?title=xaw_memory_dram_ddr_page


--
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3
Tel: (408) 626-7447
E-mail: steve.knappNO#SPAM@xilinx.com
---------------------------------
"itsme" <itsme@gmx.de> wrote in message
news:bdud1q$enh$02$1@news.t-online.com...

Hi all,
here is a quit simple, general question:
Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for
their FlipFlips?
+ This would reduce the power for the clock tree.
+ I could directly use the Data from an external DDR-DRAM

 

[Nicholas C. Weaver]

In article <gZ0Na.1998$as1.558049332@twister1.starband.net>,
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:

The Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGAs have DDR registers
as part of each I/O block.

For high-performance applications, you would want to use two outputs from
the Digital Clock Manager, one being the de-skewed, non-shifted clock output
and the de-skewed, 180 degrees phase-shifted clock output. This technique
minimizes any potential duty-cycle distortion and gives you most of the
entire half-period for your logic application.

I think the origional poster means the opposite, having the internal
registers in teh FPGA trigger on both the rising and falling clock
edge, to save power in clock distribution.

Unfortunatly, this would require even clock phases in all cases,
significantly more complex flip-flops, and I'm guessing the
power-savings in the clock distribution (now running at half speed)
would be swamped by the additional power draw within the flip-flops
themselves to allow them to trigger on both edges.

--
Nicholas C. Weaver nweaver@cs.berkeley.edu