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fl
Guest
Hi,
I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter
unsigned or signed number. When I try it with Modelsim, I find that it
insists the result be 10-bit. Otherwise, it issues a warning.
Could you explain what rule behind Modelsim to give such a warning?
Thanks,
----------------
architecture behave of example_signed_unsigned is
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal rs_SUB_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUB_RESULT : unsigned(4 downto 0) := (others => '0');
signal rs_mpy_RESULT : signed(9 downto 0) := (others => '0');
signal ru_mpy_RESULT : unsigned(9 downto 0) := (others => '0');
begin
-- Purpose: Add two numbers. Does both the signed and unsigned
-- addition for demonstration. This process is synthesizable.
p_SUM : process (i_clk, i_rst_l)
begin
if i_rst_l = '0' then -- asynchronous reset (active low)
rs_SUM_RESULT <= (others => '0');
ru_SUM_RESULT <= (others => '0');
elsif rising_edge(i_clk) then
ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b);
rs_SUM_RESULT <= signed(i_a) + signed(i_b);
end if;
end process p_SUM;
p_mpy0 : process (i_clk, i_rst_l)
begin
if i_rst_l = '0' then -- asynchronous reset (active low)
rs_mpy_RESULT <= (others => '0');
ru_mpy_RESULT <= (others => '0');
elsif rising_edge(i_clk) then
ru_mpy_RESULT <= unsigned(i_a) * unsigned(i_b);
rs_mpy_RESULT <= signed(i_a) * signed(i_b);
end if;
end process p_mpy0;
I know if 5-bit multiplies 5-bit, the result will be 9-bit, no matter
unsigned or signed number. When I try it with Modelsim, I find that it
insists the result be 10-bit. Otherwise, it issues a warning.
Could you explain what rule behind Modelsim to give such a warning?
Thanks,
----------------
architecture behave of example_signed_unsigned is
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal rs_SUB_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUB_RESULT : unsigned(4 downto 0) := (others => '0');
signal rs_mpy_RESULT : signed(9 downto 0) := (others => '0');
signal ru_mpy_RESULT : unsigned(9 downto 0) := (others => '0');
begin
-- Purpose: Add two numbers. Does both the signed and unsigned
-- addition for demonstration. This process is synthesizable.
p_SUM : process (i_clk, i_rst_l)
begin
if i_rst_l = '0' then -- asynchronous reset (active low)
rs_SUM_RESULT <= (others => '0');
ru_SUM_RESULT <= (others => '0');
elsif rising_edge(i_clk) then
ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b);
rs_SUM_RESULT <= signed(i_a) + signed(i_b);
end if;
end process p_SUM;
p_mpy0 : process (i_clk, i_rst_l)
begin
if i_rst_l = '0' then -- asynchronous reset (active low)
rs_mpy_RESULT <= (others => '0');
ru_mpy_RESULT <= (others => '0');
elsif rising_edge(i_clk) then
ru_mpy_RESULT <= unsigned(i_a) * unsigned(i_b);
rs_mpy_RESULT <= signed(i_a) * signed(i_b);
end if;
end process p_mpy0;