Why do conversion functions need to be self defined in a pro

[fl]

Hi,

I have a Matlab generated VHDL code project. It has such functions defined in
the testbench package. I am just curious about why these looks frequent used
functions need to write in such a project. It makes the test bench file very
long, not friendly reading to me.

Are there some similar functions out there accessible to me? Or, is there
some reasons left to the designer to do by themselves?

Thanks,



-- Functions
FUNCTION to_integer( x : IN std_logic) RETURN integer;
FUNCTION to_hex( x : IN std_logic) RETURN string;
FUNCTION to_hex( x : IN std_logic_vector) RETURN string;
FUNCTION to_hex( x : IN bit_vector ) RETURN string;
FUNCTION to_hex( x : IN signed ) RETURN string;
FUNCTION to_hex( x : IN unsigned ) RETURN string;
FUNCTION to_hex( x : IN real ) RETURN string;
FUNCTION SLICE( x : IN bit_vector; slice : In Integer) RETURN std_logic_vector;

 

[Brian Drummond]

On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote:

Hi,

I have a Matlab generated VHDL code project. It has such functions
defined in the testbench package. I am just curious about why these
looks frequent used functions need to write in such a project. It makes
the test bench file very long, not friendly reading to me.

Put them in a utilities package so they don't clutter up the testbench.

Are there some similar functions out there accessible to me? Or, is
there some reasons left to the designer to do by themselves?

There are libraries of functions to aid testing out there.

www.osvvm.org supports constrained random verification
https://github.com/LarsAsplund/vunit supports unit testing.

Both of these have utilities to simplify reporting, which may cover your
needs.

However http://bitvis.no/resources/utility-library-download/ may be
exactly what you are asking for.

-- Brian

 

[rickman]

On 9/29/2015 5:20 AM, Brian Drummond wrote:

On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote:

Hi,

I have a Matlab generated VHDL code project. It has such functions
defined in the testbench package. I am just curious about why these
looks frequent used functions need to write in such a project. It makes
the test bench file very long, not friendly reading to me.

Put them in a utilities package so they don't clutter up the testbench.

Are there some similar functions out there accessible to me? Or, is
there some reasons left to the designer to do by themselves?

There are libraries of functions to aid testing out there.

www.osvvm.org supports constrained random verification
https://github.com/LarsAsplund/vunit supports unit testing.

Both of these have utilities to simplify reporting, which may cover your
needs.

However http://bitvis.no/resources/utility-library-download/ may be
exactly what you are asking for.

I think the OP is using a utility to generate a test bench and it is
adding the various functions which are *not* part of any of the
conventional packages. So they stick them in the main file of the test
bench. If he moves these functions to a package he will need to do the
same work every time he generates the test bench again.

--

Rick

 

[Brian Drummond]

On Tue, 29 Sep 2015 12:00:12 -0400, rickman wrote:

On 9/29/2015 5:20 AM, Brian Drummond wrote:
On Mon, 28 Sep 2015 09:33:37 -0700, fl wrote:

Hi,

I have a Matlab generated VHDL code project. It has such functions
defined in the testbench package. I am just curious about why these
looks frequent used functions need to write in such a project. It
makes the test bench file very long, not friendly reading to me.

Put them in a utilities package so they don't clutter up the testbench.

I think the OP is using a utility to generate a test bench and it is
adding the various functions which are *not* part of any of the
conventional packages. So they stick them in the main file of the test
bench. If he moves these functions to a package he will need to do the
same work every time he generates the test bench again.

Ah, then he has a Matlab problem rather than a VHDL problem. Hopefully
someone else can help.

-- Brian