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why assignment to a single bit of a reg report a error?...

H

Hill Stone

Guest
четвер, 10 квітня 1997 р. о 08:00:00 UTC+1 David Emrich пише:
lzh wrote:
...
module test(a,b);
input a;
output [1:0] b;
reg [1:0] b;
always @(a)
begin
assign b[0]=a;
assign b[1]=!a;
end
endmodule

when i use Cadence Verilog-XL to compile it ,Verilog-XL report a
error \"Illegal
left-hand-side in assignment\",but when i use Veriwell to compile it ,it
does work!
and if i use \"assign b={a,!a};\"instead of it,the Verilog-XL can compile it
without any error,can anybody explain why?
Bit select on the left side of a continuous procedural assignment is
prohibited in the OVI 2.0 Verilog LRM.
David Emrich
Exemplar Logic
emr...@exemplar.com
.
This may be a temporary error. I came across this. This problem is easy to fix. My assignment with <a href=\"https://www.nursingpaper.com/\">writing nursing papers</a> is especially troublesome for me. I\'m so tired of it that I just want to quit. But it is stopped me by the fact that there is very little time left before graduation.
 
H

Hill Stone

Guest
четвер, 10 квітня 1997 р. о 08:00:00 UTC+1 David Emrich пише:
lzh wrote:
...
module test(a,b);
input a;
output [1:0] b;
reg [1:0] b;
always @(a)
begin
assign b[0]=a;
assign b[1]=!a;
end
endmodule

when i use Cadence Verilog-XL to compile it ,Verilog-XL report a
error \"Illegal
left-hand-side in assignment\",but when i use Veriwell to compile it ,it
does work!
and if i use \"assign b={a,!a};\"instead of it,the Verilog-XL can compile it
without any error,can anybody explain why?
Bit select on the left side of a continuous procedural assignment is
prohibited in the OVI 2.0 Verilog LRM.
David Emrich
Exemplar Logic
emr...@exemplar.com
.
This may be a temporary error. I came across this. This problem is easy to fix. My assignment with writing nursing papers is especially troublesome for me. I\'m so tired of it that I just want to quit. But it is stopped me by the fact that there is very little time left before graduation.
 
H

Hill Stone

Guest
четвер, 10 квітня 1997 р. о 08:00:00 UTC+1 David Emrich пише:
lzh wrote:
...
module test(a,b);
input a;
output [1:0] b;
reg [1:0] b;
always @(a)
begin
assign b[0]=a;
assign b[1]=!a;
end
endmodule

when i use Cadence Verilog-XL to compile it ,Verilog-XL report a
error \"Illegal
left-hand-side in assignment\",but when i use Veriwell to compile it ,it
does work!
and if i use \"assign b={a,!a};\"instead of it,the Verilog-XL can compile it
without any error,can anybody explain why?
Bit select on the left side of a continuous procedural assignment is
prohibited in the OVI 2.0 Verilog LRM.
David Emrich
Exemplar Logic
emr...@exemplar.com
.
This may be a temporary error. I came across this too. This problem is easy to fix. My assignment with writing nursing papers is especially troublesome for me more. I\'m so tired of it that I just want to quit. Only https://www.nursingpaper.com/ help me out and I am happy with the fact that there is very little time left before the graduation ceremony.
 
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