Where does the XOR come to play?

[fl]

Hi,

I am working on a LUT in a project. The input entries are signed. In order to
same memory, only positive entries are considered in the LUT. Thus, negative
input is first converted to positive data. Then, the result is converted back
to negative. These input data is 2's complementary format.

On the original paper, it had the following description. I am still new to
FPGA. I am not clear about where and how to use 'XOR' in the process.

Could you explain it to me? Thanks a lot.



Further reduction in the memory size is achieved by storing only positive
values in the LUT. The sign of the division result can be evaluated by an XOR
gate.

 

[Michael Kellett]

fl:

Hi,

I am working on a LUT in a project. The input entries are signed. In
order to
same memory, only positive entries are considered in the LUT. Thus,
negative
input is first converted to positive data. Then, the result is
converted back
to negative. These input data is 2's complementary format.

On the original paper, it had the following description. I am still
new to
FPGA. I am not clear about where and how to use 'XOR' in the process.

Could you explain it to me? Thanks a lot.



Further reduction in the memory size is achieved by storing only
positive
values in the LUT. The sign of the division result can be evaluated
by an XOR
gate.

XORing the signs of the multiplier and multiplicand to get the sign of
the answer ?

MK

 

[glen herrmannsfeldt]

fl <rxjwg98@gmail.com> wrote:

I am working on a LUT in a project. The input entries are signed.
In order to same memory, only positive entries are considered
in the LUT. Thus, negative input is first converted to positive data.
Then, the result is converted back to negative.
These input data is 2's complementary format.

On the original paper, it had the following description.
I am still new to FPGA. I am not clear about where and how
to use 'XOR' in the process.

Could you explain it to me? Thanks a lot.

Sounds like you need a twos complement absolute value.

If the input value is positive, it is fine.

If negative, invert all the bits (with XOR) and add one.

In the end, to convert back to twos complement, if the result
should be negative invert the bits (XOR again) and add one.

-- glen

 

[rickman]

On 9/30/2015 8:44 AM, fl wrote:

Hi,

I am working on a LUT in a project. The input entries are signed. In order to
same memory, only positive entries are considered in the LUT. Thus, negative
input is first converted to positive data. Then, the result is converted back
to negative. These input data is 2's complementary format.

On the original paper, it had the following description. I am still new to
FPGA. I am not clear about where and how to use 'XOR' in the process.

Could you explain it to me? Thanks a lot.



Further reduction in the memory size is achieved by storing only positive
values in the LUT. The sign of the division result can be evaluated by an XOR
gate.

Are you doing a division by LUT? What are the sizes of your input
operands?

The sign of the output will be the XOR of the sign of the two inputs to
a division, just as Michael indicated for a multiplication.

--

Rick