What is wrong tihis function code?

[fl]

Hi,
I am learning to write a VHDL function code. Modelsim complains that something
wrong at function line. The code is:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
function s1qrt ( d : unsigned ) return unsigned is
variable a : unsigned(31 downto 0) := d; --original input.
variable q : unsigned(15 downto 0) := (others => '0'); --result.
variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder.
variable i : integer := 0;
begin
-- for i in 0 to 15 loop
right(0) := '1';
right(1) := r(17);
right(17 downto 2) := q;
left(1 downto 0) := a(31 downto 30);
left(17 downto 2) := r(15 downto 0);
a(31 downto 2) := a(29 downto 0); --shifting by 2 bit.
if ( r(17) = '1') then
r := left + right;
else
r := left - right;
end if;

q(15 downto 1) := q(14 downto 0);
q(0) := not r(17);
-- end loop;
return q;

end s1qrt;

I cannot make it out what is wrong. Could you help me?

Thanks,

 

[KJ]

On Tuesday, April 7, 2015 at 11:47:37 AM UTC-4, fl wrote:

Hi,
I am learning to write a VHDL function code. Modelsim complains that something
wrong at function line. The code is:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
function s1qrt ( d : unsigned ) return unsigned is
variable a : unsigned(31 downto 0) := d; --original input.
variable q : unsigned(15 downto 0) := (others => '0'); --result.
variable left, right, r : unsigned(17 downto 0):= (others => '0'); --input to adder/sub.r-remainder.
variable i : integer := 0;
begin
-- for i in 0 to 15 loop
right(0) := '1';
right(1) := r(17);
right(17 downto 2) := q;
left(1 downto 0) := a(31 downto 30);
left(17 downto 2) := r(15 downto 0);
a(31 downto 2) := a(29 downto 0); --shifting by 2 bit.
if ( r(17) = '1') then
r := left + right;
else
r := left - right;
end if;

q(15 downto 1) := q(14 downto 0);
q(0) := not r(17);
-- end loop;
return q;

end s1qrt;

I cannot make it out what is wrong. Could you help me?

Thanks,

Functions must always be embedded within something such as a package or an entity/architecture. The general hierarchy is:
- entity: This will define the interface (i.e. inputs and outputs) of a design
- architecture: This defines the logic implemented given the entity I/O.

A function can be defined within an architecture or within a process. Below shows where it would go. Functions can also be defined in packages, but let's defer that for now

entity foo is port map(....)
end foo;

architecture rtl of foo is
function s1qrt ( d : unsigned ) return unsigned is
...
end function s1qrt;
begin
process(...)
function s1qrt ( d : unsigned ) return unsigned is
...
end function s1qrt;
begin
end process;
end rtl;

Kevin Jennings