What is one element of a signed array?

[fl]

Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


Thanks for the kind replies.

..................
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal bit0 : bit;

 

[fl]

On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote:

Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


Thanks for the kind replies.

.................
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal bit0 : bit;

Using to_bit seems to work in my previous post. But for convert
rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different
types and widths. What is your method?
Thanks,




type BYTE is array (0 to 7) of BIT;
signal sig_byte : BYTE;
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');

 

[KJ]

On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote:

Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);

You haven't said what you're trying to do nor have you said in what way you are finding something 'wrong'. I can guess that because you call the signal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for whatever reason you've selected bit 1 instead.

bit0 <= rs_SUM_RESULT(0);

Kevin

 

[rickman]

On 9/30/2015 8:05 AM, fl wrote:

On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote:
Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


Thanks for the kind replies.

.................
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal bit0 : bit;

Using to_bit seems to work in my previous post. But for convert
rs_SUM_RESULT to BYTE, I don't see a simple way yet. They are different
types and widths. What is your method?
Thanks,




type BYTE is array (0 to 7) of BIT;
signal sig_byte : BYTE;
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');

This begs the question of why you need to use a bit type? They don't do
anything the signed type won't do.

I don't think there are any standard conversion routines for signed or
unsigned to a bit vector. You will need to write one. It is just a
function that takes a signed value as input and returns a bit vector
with the same width. It will need a loop that assigns each bit one at a
time using the conversion you found for the single bit. The input and
output can be unconstrained which means it will work for any width of data.

--

Rick

 

[fl]

On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote:

On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote:
Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


You haven't said what you're trying to do nor have you said in what way you are finding something 'wrong'. I can guess that because you call the signal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for whatever reason you've selected bit 1 instead.

bit0 <= rs_SUM_RESULT(0);

Kevin

Excuse me. I didn't say the question clearly.
My original intention was to convert array larger or smaller to BYTE.
It was inspired from an online code. With rickman's new post, I know the
less important role of bit vector. The conversion is to use a for loop on
bit level. That's all to my question. With several VHDL type coding
projects, I feel it is clear and manageable after several tryings on it in
the past. Thanks, you folks.



type BYTE is array (0 to 7) of BIT;
signal sig_byte : BYTE;
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
rs_SUM_RESULT

 

[rickman]

On 9/30/2015 9:55 PM, fl wrote:

On Wednesday, September 30, 2015 at 12:11:28 PM UTC-4, KJ wrote:
On Wednesday, September 30, 2015 at 7:54:19 AM UTC-4, fl wrote:
Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


You haven't said what you're trying to do nor have you said in what way you are finding something 'wrong'. I can guess that because you call the signal 'bit0', that you like bit0 to be bit 0 from 'rs_SUM_RESULT' but for whatever reason you've selected bit 1 instead.

bit0 <= rs_SUM_RESULT(0);

Kevin

Excuse me. I didn't say the question clearly.
My original intention was to convert array larger or smaller to BYTE.
It was inspired from an online code. With rickman's new post, I know the
less important role of bit vector. The conversion is to use a for loop on
bit level. That's all to my question. With several VHDL type coding
projects, I feel it is clear and manageable after several tryings on it in
the past. Thanks, you folks.



type BYTE is array (0 to 7) of BIT;
signal sig_byte : BYTE;
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
rs_SUM_RESULT

Not sure if your post was cut off.

I never use bits, so I am not so familiar with that data type, but it
seems the std_logic_1164 library has conversion functions between bit or
bit_vector and std_logic or std_logic_vector respectively. That would
make a conversion with signed and unsigned trivial without using looping
or making your own function.

Are these problems homework for a class? If so, I think you are getting
the right kind of advice to help you see the solution rather than just
being given the answers.

BTW, BYTE can be defined this way too...

type BYTE is bit_vector (7 downto 0);

This will work with all the conversion functions while I'm not sure if
your BYTE declaration will. Like I said, I'm a bit rusty with this stuff.

--

Rick

 

[Thomas Stanka]

Am Mittwoch, 30. September 2015 13:54:19 UTC+2 schrieb fl:
[..]

signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal bit0 : bit;

This depends on _your_ definition of signed. All standardised definitions use (un)signed as vector of std_logic.

so the code would work if bit0 is of type std_logic, should even work with std_ulogic. Else you need to convert the result of singedSignal(1) to bit before assigning to a bit value.

 

[Rob Gaddi]

On Wed, 30 Sep 2015 04:54:14 -0700, fl wrote:

Hi,

After a few progress on VHDL type conversion, I have new difficulties on
the element access of an unsigned array. Please see the below example.

How can I get the element of rs_SUM_RESULT ?

I find this is wrong:
bit0 <= rs_SUM_RESULT(1);


Thanks for the kind replies.

.................
signal rs_SUM_RESULT : signed(4 downto 0) := (others => '0');
signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');
signal bit0 : bit;

Assuming that you're using the signed/unsigned from ieee.numeric_std?
std_logic.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.