what are the possible reasons that successful pre-synthesis

[walala]

Dear all,

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
internal nodes have "1", and the other internal nodes have "X"... but the
internal nodes were stuck with their values: the "0"s were always "0", the
"1"s were always "1", the "X"s were always "X"...

Worth noting is that I follow the same workflow for some very small designs,
it worked perfectly... but now it failed for medium-big size design...

I feel the errors are so systemetic, which may be caused by some hidden
tricks(for large size design) in Synopsys DC that I did not know...

Can anybody help me out of this swamp?

Thanks:

--------------------------------------------------------------
My script file:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct.log {
analyze -format vhdl -lib WORK {myidct.vhd}
elaborate myidct -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "clk" -name "clk" -period 10
compile -map_effort medium
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
reports/\$current_d
esign.rep
report_area >> reports/\$current_design.rep
change_names -rules vhdl
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
plot -hierarchy -output "schematic/\$current_design.ps"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

---------------------------------------------------------

 

[Chi]

When you say your design is large I assume it has hierarchy. In your
script,
you remove all hierarchies which allows Design Compiler to optimize
logics
across the old hierarchy assumed they still exist. Simulation mismatch
then
could happen if your stimulus is applied to the hierarchy signal pins
which
may or may have changed during optimization. You can easily rule this
out by
removing the "ungroup -all -flatten" command from your script. If this
is the
case that cause mismatch but you want to flatten your design then you
must rewrite your test bench.

Good luck,
Chi

"walala" <mizhael@yahoo.com> wrote in message news:<bjfium$693$1@mozo.cc.purdue.edu>...

Dear all,

I have run the pre-synthesis successfully using Modelsim successfully, and
then I do a Synopsys DC synthesis successfully(only have some warnings, no
errors), but when it came to post-synthesis using Modelsim, the outputs
became "XXXXXXXXXXXXX"(no values); some internal nodes have "0", some
internal nodes have "1", and the other internal nodes have "X"... but the
internal nodes were stuck with their values: the "0"s were always "0", the
"1"s were always "1", the "X"s were always "X"...

Worth noting is that I follow the same workflow for some very small designs,
it worked perfectly... but now it failed for medium-big size design...

I feel the errors are so systemetic, which may be caused by some hidden
tricks(for large size design) in Synopsys DC that I did not know...

Can anybody help me out of this swamp?

Thanks:

--------------------------------------------------------------
My script file:

$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct.log {
analyze -format vhdl -lib WORK {myidct.vhd}
elaborate myidct -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "clk" -name "clk" -period 10
compile -map_effort medium
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1
reports/\$current_d
esign.rep
report_area >> reports/\$current_design.rep
change_names -rules vhdl
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
plot -hierarchy -output "schematic/\$current_design.ps"
echo "\nScript Done\n"
echo "\nChecking Design\n"
check_design
}
!

---------------------------------------------------------