VHDL

Guest
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


---------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity Lane is
port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic;

DATA_IN : IN std_logic;

FPP_SEC_EN : IN std_logic;

FPP_TURN_SEL : IN std_logic;

FPP_CORE_SEL : IN std_logic;

FPP_REGP_BYP : IN std_logic;

FPP_SOURCE_SEL : IN std_logic;

FPP_REGN_BYP : IN std_logic;

FPP_PRI_EN : IN std_logic;

Primary_Port : INOUT std_logic;

Secondary_Port : INOUT std_logic;

FPP_TO_CORE : OUT std_logic;

DATA_OUT : OUT std_logic
);
end Lane;

architecture archLane of Lane is



component Buf
port (
A : IN std_logic;
Y : OUT std_logic
);
end component;

component BufX
port (
A : IN std_logic;
en : in std_logic;
Y : OUT std_logic
);
end component;


component Mux
port (
Sel : IN std_logic;
E : IN std_logic;
F : IN std_logic;
Z : OUT std_logic
);
end component;


component FlipFlopP
port (
CLK : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
end component;


component FlipFlopN
port (
CLK : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
end component;

signal Sec_buf_in_to_Mux6 : std_logic;
signal Sel_BufX_in_to_Mux3 : std_logic;
signal Sec_Pri_Buf_IN_TO_MUX6 :std_logic;
signal Sec_Pri_BufY_IN_TO_MUX1 : std_logic;
signal sig_from_Mux1_ff1_to_Mux3_ff3 : std_logic;
signal sig_from_Mux1_to_FF1 : std_logic;
signal sig_from_Mux5_to_FF2_Mux2 :std_logic;
signal sig_from_FF2_to_Mux2 : std_logic;
signal sig_from_Mux3_to_FF3 : std_logic;
signal sig_from_Mux4_to_Mux5 : std_logic;
signal FPP_TO_CORE_INT : std_logic;

begin
FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE


Sec_Buf_In : Buf
port map ( A => Secondary_Port,
Y => Sec_buf_in_to_Mux6);

Sec_BufX_Out : BufX
port map ( A => Sel_BufX_in_to_Mux3,
en => FPP_SEC_EN ,
Y => Secondary_Port);

Pri_Buf_In : Buf
port map ( A => Primary_Port,
Y => Sec_Pri_Buf_IN_TO_MUX6);

Pri_BufX_Out : BufX
port map ( A => Sec_Pri_BufY_IN_TO_MUX1,
en => FPP_PRI_EN,
Y => Primary_Port);

MUX1 : Mux
port map ( E => Sig_from_Mux1_ff1_to_Mux3_ff3,
F => sig_from_Mux1_to_FF1,
Z => Sec_Pri_BufY_IN_TO_MUX1,
Sel => FPP_REGN_BYP);

MUX2 : Mux
port map ( E => sig_from_Mux5_to_FF2_Mux2,
F => sig_from_FF2_to_Mux2,
Z => DATA_OUT,
Sel => FPP_REGP_BYP
);

MUX3 : Mux
port map ( E => sig_from_Mux1_ff1_to_Mux3_ff3,
F => sig_from_Mux3_to_FF3,
Z => Sel_BufX_in_to_Mux3,
Sel => FPP_REGN_BYP
);

MUX4 : Mux
port map ( E => DATA_IN,
F => FPP_FROM_CORE,
Z => sig_from_Mux4_to_Mux5,
Sel => FPP_TURN_SEL
);

MUX5 : Mux
port map ( E => sig_from_Mux4_to_Mux5,
F => FPP_TO_CORE_INT,
Z => sig_from_Mux5_to_FF2_Mux2,
Sel => FPP_CORE_SEL
);

MUX6 : Mux
port map ( E => Sec_buf_in_to_Mux6,
F => Sec_pri_buf_in_to_Mux6,
Z => FPP_TO_CORE_INT,
Sel => FPP_SOURCE_SEL
);

Flipflop1 : FlipFlopN
port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3,
D => sig_from_Mux1_to_FF1,
CLK => FPP_CLK_IN
);

Flipflop2 : FlipFlopP
port map ( Q => sig_from_Mux5_to_FF2_Mux2,
D => sig_from_FF2_to_Mux2,
CLK => FPP_CLK_IN
);

Flipflop3 : FlipFlopN
port map ( Q => sig_from_Mux1_ff1_to_Mux3_ff3,
D => sig_from_Mux3_to_FF3,
CLK => FPP_CLK_IN
);

end archLane;



et mon testbench

library ieee;
use ieee.std_logic_1164.all;

entity testPrimToSecCase1 is
end testPrimToSecCase1;

architecture archPrimToSecTest of testPrimToSecCase1 is

component Lane
Port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic;

DATA_IN : IN std_logic;

FPP_SEC_EN : IN std_logic;

FPP_TURN_SEL : IN std_logic;

FPP_CORE_SEL : IN std_logic;

FPP_REGP_BYP : IN std_logic;

FPP_SOURCE_SEL : IN std_logic;

FPP_REGN_BYP : IN std_logic;

FPP_PRI_EN : IN std_logic;

Primary_Port : INOUT std_logic;

Secondary_Port : INOUT std_logic;

DATA_OUT : OUT std_logic;

FPP_TO_CORE : OUT std_logic
);
end component;

signal S_FPP_CLK_IN : std_logic;

signal S_FPP_FROM_CORE : std_logic;

signal S_DATA_IN : std_logic;

signal S_FPP_SEC_EN : std_logic;

signal S_FPP_TURN_SEL : std_logic;

signal S_FPP_CORE_SEL : std_logic;

signal S_FPP_REGP_BYP : std_logic;

signal S_FPP_SOURCE_SEL : std_logic;

signal S_FPP_REGN_BYP : std_logic;

signal S_FPP_PRI_EN : std_logic;

signal S_Primary_Port : std_logic;

signal S_Secondary_Port : std_logic;

signal s_FPP_TO_CORE_INT : std_logic;

FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE

begin


U : Lane
port map (
S_FPP_CLK_IN,
S_FPP_FROM_CORE,
S_DATA_IN,
S_FPP_SEC_EN,
S_FPP_TURN_SEL,
S_FPP_CORE_SEL,
S_FPP_REGP_BYP,
S_FPP_SOURCE_SEL,
S_FPP_REGN_BYP,
S_FPP_PRI_EN,
S_Primary_Port,
S_Secondary_Port
);


processClock : process
begin

S_FPP_CLK_IN <= '0';
wait for 10 ns;
S_FPP_CLK_IN <= '1';
wait for 10 ns;

end process processClock;

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck
 
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:
Click to expand...

[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck
Click to expand...

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor
 
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor
Click to expand...

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck
 
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck
Click to expand...

What do you see in your simulation?

--

Rick
 
Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman:
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck

What do you see in your simulation?

--

Rick
hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving.
Click to expand...

library ieee;
use ieee.std_logic_1164.all;

entity testPrimToSecCase1 is
end testPrimToSecCase1;

architecture archPrimToSecTest of testPrimToSecCase1 is

component Lane
Port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic; -- (j)

DATA_IN : IN std_logic; -- (K)

FPP_SEC_EN : IN std_logic; -- (b)

FPP_TURN_SEL : IN std_logic; -- (c)

FPP_CORE_SEL : IN std_logic; -- (d)

FPP_REGP_BYP : IN std_logic; -- (e)

FPP_SOURCE_SEL : IN std_logic; -- (f)

FPP_REGN_BYP : IN std_logic; -- (g)

FPP_PRI_EN : IN std_logic; -- (h)

Primary_Port : INOUT std_logic; -- (i)

Secondary_Port : INOUT std_logic; -- (a)

DATA_OUT : OUT std_logic;

FPP_TO_CORE : OUT std_logic
);
end component;

----------------------- INPUT ------------------
signal S_FPP_CLK_IN : std_logic;

signal S_FPP_FROM_CORE : std_logic; -- (j)

signal S_DATA_IN : std_logic; -- (K)

signal S_FPP_SEC_EN : std_logic; -- (b)

signal S_FPP_TURN_SEL : std_logic; -- (c)

signal S_FPP_CORE_SEL : std_logic; -- (d)

signal S_FPP_REGP_BYP : std_logic; -- (e)

signal S_FPP_SOURCE_SEL : std_logic; -- (f)

signal S_FPP_REGN_BYP : std_logic; -- (g)

signal S_FPP_PRI_EN : std_logic; -- (h)

-------------- InOutput ------------------------
signal S_Primary_Port : std_logic; -- (i)

signal S_Secondary_Port : std_logic; -- (a)

----------------- OUTPUT -----------------------
signal S_FPP_TO_CORE_INT : std_logic;

signal S_DATA_OUT : std_logic; -- (k)

--FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE

begin

-- Komponent Instanzierung mit Verdrahtung

U : Lane
port map (
S_FPP_CLK_IN,

S_FPP_FROM_CORE, -- j
S_DATA_IN, -- k
S_FPP_SEC_EN, -- b
S_FPP_TURN_SEL, -- c
S_FPP_CORE_SEL, -- d
S_FPP_REGP_BYP, -- e
S_FPP_SOURCE_SEL, -- f
S_FPP_REGN_BYP, -- g
S_FPP_PRI_EN, -- h
S_Primary_Port, -- i
S_Secondary_Port, -- a
S_DATA_OUT,
S_FPP_TO_CORE_INT
);


processClock : process
begin

S_FPP_CLK_IN <= '0';
wait for 10 ns;
S_FPP_CLK_IN <= '1';
wait for 10 ns;

end process processClock;

Stimuli : process
begin

S_FPP_FROM_CORE <= '0'; -- j
S_DATA_IN <= '0'; -- k
S_FPP_SEC_EN <= '0'; -- b
S_FPP_TURN_SEL <= '0'; -- c
S_FPP_CORE_SEL <= '0'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h
S_Primary_Port <= ''; -- i
S_Secondary_Port <= '0'; -- a

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-'; -- j
S_DATA_IN <= '-'; -- k
S_FPP_SEC_EN <= '1'; -- b
S_FPP_TURN_SEL <= '-'; -- c
S_FPP_CORE_SEL <= '1'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h

--wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '0';

S_Primary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
 
Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman:
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck

What do you see in your simulation?

--

Rick
Click to expand...

hello Rick how can i sent you the file. I try without success.
 
Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com:
Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman:
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck

What do you see in your simulation?

--

Rick
hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving.

library ieee;
use ieee.std_logic_1164.all;

entity testPrimToSecCase1 is
end testPrimToSecCase1;

architecture archPrimToSecTest of testPrimToSecCase1 is

component Lane
Port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic; -- (j)

DATA_IN : IN std_logic; -- (K)

FPP_SEC_EN : IN std_logic; -- (b)

FPP_TURN_SEL : IN std_logic; -- (c)

FPP_CORE_SEL : IN std_logic; -- (d)

FPP_REGP_BYP : IN std_logic; -- (e)

FPP_SOURCE_SEL : IN std_logic; -- (f)

FPP_REGN_BYP : IN std_logic; -- (g)

FPP_PRI_EN : IN std_logic; -- (h)

Primary_Port : INOUT std_logic; -- (i)

Secondary_Port : INOUT std_logic; -- (a)

DATA_OUT : OUT std_logic;

FPP_TO_CORE : OUT std_logic
);
end component;

----------------------- INPUT ------------------
signal S_FPP_CLK_IN : std_logic;

signal S_FPP_FROM_CORE : std_logic; -- (j)

signal S_DATA_IN : std_logic; -- (K)

signal S_FPP_SEC_EN : std_logic; -- (b)

signal S_FPP_TURN_SEL : std_logic; -- (c)

signal S_FPP_CORE_SEL : std_logic; -- (d)

signal S_FPP_REGP_BYP : std_logic; -- (e)

signal S_FPP_SOURCE_SEL : std_logic; -- (f)

signal S_FPP_REGN_BYP : std_logic; -- (g)

signal S_FPP_PRI_EN : std_logic; -- (h)

-------------- InOutput ------------------------
signal S_Primary_Port : std_logic; -- (i)

signal S_Secondary_Port : std_logic; -- (a)

----------------- OUTPUT -----------------------
signal S_FPP_TO_CORE_INT : std_logic;

signal S_DATA_OUT : std_logic; -- (k)

--FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE

begin

-- Komponent Instanzierung mit Verdrahtung

U : Lane
port map (
S_FPP_CLK_IN,

S_FPP_FROM_CORE, -- j
S_DATA_IN, -- k
S_FPP_SEC_EN, -- b
S_FPP_TURN_SEL, -- c
S_FPP_CORE_SEL, -- d
S_FPP_REGP_BYP, -- e
S_FPP_SOURCE_SEL, -- f
S_FPP_REGN_BYP, -- g
S_FPP_PRI_EN, -- h
S_Primary_Port, -- i
S_Secondary_Port, -- a
S_DATA_OUT,
S_FPP_TO_CORE_INT
);


processClock : process
begin

S_FPP_CLK_IN <= '0';
wait for 10 ns;
S_FPP_CLK_IN <= '1';
wait for 10 ns;

end process processClock;

Stimuli : process
begin

S_FPP_FROM_CORE <= '0'; -- j
S_DATA_IN <= '0'; -- k
S_FPP_SEC_EN <= '0'; -- b
S_FPP_TURN_SEL <= '0'; -- c
S_FPP_CORE_SEL <= '0'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h
S_Primary_Port <= ''; -- i
S_Secondary_Port <= '0'; -- a

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-'; -- j
S_DATA_IN <= '-'; -- k
S_FPP_SEC_EN <= '1'; -- b
S_FPP_TURN_SEL <= '-'; -- c
S_FPP_CORE_SEL <= '1'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h

--wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '0';

S_Primary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
Click to expand...

is there anyway to sent you the file?
 
fwetie@googlemail.com wrote:
Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman:
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:

[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck
Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor
danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck
What do you see in your simulation?

--

Rick
hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving.

library ieee;
use ieee.std_logic_1164.all;

entity testPrimToSecCase1 is
end testPrimToSecCase1;

architecture archPrimToSecTest of testPrimToSecCase1 is

component Lane
Port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic; -- (j)

DATA_IN : IN std_logic; -- (K)

FPP_SEC_EN : IN std_logic; -- (b)

FPP_TURN_SEL : IN std_logic; -- (c)

FPP_CORE_SEL : IN std_logic; -- (d)

FPP_REGP_BYP : IN std_logic; -- (e)

FPP_SOURCE_SEL : IN std_logic; -- (f)

FPP_REGN_BYP : IN std_logic; -- (g)

FPP_PRI_EN : IN std_logic; -- (h)

Primary_Port : INOUT std_logic; -- (i)

Secondary_Port : INOUT std_logic; -- (a)

DATA_OUT : OUT std_logic;

FPP_TO_CORE : OUT std_logic
);
end component;

----------------------- INPUT ------------------
signal S_FPP_CLK_IN : std_logic;

signal S_FPP_FROM_CORE : std_logic; -- (j)

signal S_DATA_IN : std_logic; -- (K)

signal S_FPP_SEC_EN : std_logic; -- (b)

signal S_FPP_TURN_SEL : std_logic; -- (c)

signal S_FPP_CORE_SEL : std_logic; -- (d)

signal S_FPP_REGP_BYP : std_logic; -- (e)

signal S_FPP_SOURCE_SEL : std_logic; -- (f)

signal S_FPP_REGN_BYP : std_logic; -- (g)

signal S_FPP_PRI_EN : std_logic; -- (h)

-------------- InOutput ------------------------
signal S_Primary_Port : std_logic; -- (i)

signal S_Secondary_Port : std_logic; -- (a)

----------------- OUTPUT -----------------------
signal S_FPP_TO_CORE_INT : std_logic;

signal S_DATA_OUT : std_logic; -- (k)

--FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE

begin

-- Komponent Instanzierung mit Verdrahtung

U : Lane
port map (
S_FPP_CLK_IN,

S_FPP_FROM_CORE, -- j
S_DATA_IN, -- k
S_FPP_SEC_EN, -- b
S_FPP_TURN_SEL, -- c
S_FPP_CORE_SEL, -- d
S_FPP_REGP_BYP, -- e
S_FPP_SOURCE_SEL, -- f
S_FPP_REGN_BYP, -- g
S_FPP_PRI_EN, -- h
S_Primary_Port, -- i
S_Secondary_Port, -- a
S_DATA_OUT,
S_FPP_TO_CORE_INT
);


processClock : process
begin

S_FPP_CLK_IN <= '0';
wait for 10 ns;
S_FPP_CLK_IN <= '1';
wait for 10 ns;

end process processClock;

Stimuli : process
begin

S_FPP_FROM_CORE <= '0'; -- j
S_DATA_IN <= '0'; -- k
S_FPP_SEC_EN <= '0'; -- b
S_FPP_TURN_SEL <= '0'; -- c
S_FPP_CORE_SEL <= '0'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h
S_Primary_Port <= ''; -- i
S_Secondary_Port <= '0'; -- a

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-'; -- j
S_DATA_IN <= '-'; -- k
S_FPP_SEC_EN <= '1'; -- b
S_FPP_TURN_SEL <= '-'; -- c
S_FPP_CORE_SEL <= '1'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h

--wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '0';

S_Primary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
Click to expand...

You still have a problematic wait in your "Stimuli" process:

wait until S_FPP_CLK_IN <= '1';

This literaly means "wait until S_FPP_CLK_IN is less than or equal to 1"
and since the clock will only have values 0 or 1, it will always be
true. Therefore the wait does not actually delay the next set of
assignments until the clock is high, rather it happens immediately
at time zero. Furthermore this sort of wait is problematic when
you are trying to stimulate a clocked process and want to ensure
that the stimulus happens a "delta" delay after the rising clock
edge. You should really wait for an event. either:

wait until S_FPP_CLK_IN'event and S_FPP_CLK_IN = '1';

or:

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor
 
On 10/5/2015 9:55 AM, fwetie@googlemail.com wrote:
Am Montag, 5. Oktober 2015 15:34:21 UTC+2 schrieb fwe...@googlemail.com:
Am Samstag, 3. Oktober 2015 12:29:52 UTC+2 schrieb rickman:
On 10/3/2015 4:35 AM, fwetie@googlemail.com wrote:
Am Freitag, 2. Oktober 2015 21:20:35 UTC+2 schrieb Gabor Sz:
fwetie@googlemail.com wrote:
hello,
please i am looking for someone who can help me to solve my pb.
this is my code :

Bonjour a tous,
je cherche de l'aide pour mon projet sur VHDL:
mon testBench ne fonctionne pas correctement je voudrais de l'aide s'il vous plait.
voici mes codes:


[snip]

Stimuli : process
begin

S_FPP_FROM_CORE <= '0';
S_DATA_IN <= '0';
S_FPP_SEC_EN <= '0';
S_FPP_TURN_SEL <= '0';
S_FPP_CORE_SEL <= '0';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';
S_Primary_Port <= '0';
S_Secondary_Port <= '0';

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-';
S_DATA_IN <= '-';
S_FPP_SEC_EN <= '1';
S_FPP_TURN_SEL <= '-';
S_FPP_CORE_SEL <= '1';
S_FPP_REGP_BYP <= '0';
S_FPP_SOURCE_SEL <= '0';
S_FPP_REGN_BYP <= '0';
S_FPP_PRI_EN <= '0';

wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '1';

S_Secondary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;
i am looking for sombody to correct my testbench.
thanks you for your help.
Franck

Well, you didn't give much of a description of why the testbench does
not function correctly, but my guess is that you wanted to wait for
edges of the clock and not levels. Also it's unlikely that you
want to wait for a clock signal to be "less than or equal to 1"
even if you did want to check for a level. Probably something like

wait until rising_edge (S_FPP_CLK_IN);

--
Gabor

danke Gabor my pb is this i want to sent data from Primary_Port to Secondary_Port and i have to pass throught 4 mux. thnaks for you response
Franck

What do you see in your simulation?

--

Rick
hello Rick in the simulation when i set the data like this with the rising edge i hae to see in the output the input i have giving.

library ieee;
use ieee.std_logic_1164.all;

entity testPrimToSecCase1 is
end testPrimToSecCase1;

architecture archPrimToSecTest of testPrimToSecCase1 is

component Lane
Port (
FPP_CLK_IN : IN std_logic;

FPP_FROM_CORE : IN std_logic; -- (j)

DATA_IN : IN std_logic; -- (K)

FPP_SEC_EN : IN std_logic; -- (b)

FPP_TURN_SEL : IN std_logic; -- (c)

FPP_CORE_SEL : IN std_logic; -- (d)

FPP_REGP_BYP : IN std_logic; -- (e)

FPP_SOURCE_SEL : IN std_logic; -- (f)

FPP_REGN_BYP : IN std_logic; -- (g)

FPP_PRI_EN : IN std_logic; -- (h)

Primary_Port : INOUT std_logic; -- (i)

Secondary_Port : INOUT std_logic; -- (a)

DATA_OUT : OUT std_logic;

FPP_TO_CORE : OUT std_logic
);
end component;

----------------------- INPUT ------------------
signal S_FPP_CLK_IN : std_logic;

signal S_FPP_FROM_CORE : std_logic; -- (j)

signal S_DATA_IN : std_logic; -- (K)

signal S_FPP_SEC_EN : std_logic; -- (b)

signal S_FPP_TURN_SEL : std_logic; -- (c)

signal S_FPP_CORE_SEL : std_logic; -- (d)

signal S_FPP_REGP_BYP : std_logic; -- (e)

signal S_FPP_SOURCE_SEL : std_logic; -- (f)

signal S_FPP_REGN_BYP : std_logic; -- (g)

signal S_FPP_PRI_EN : std_logic; -- (h)

-------------- InOutput ------------------------
signal S_Primary_Port : std_logic; -- (i)

signal S_Secondary_Port : std_logic; -- (a)

----------------- OUTPUT -----------------------
signal S_FPP_TO_CORE_INT : std_logic;

signal S_DATA_OUT : std_logic; -- (k)

--FPP_TO_CORE <= FPP_TO_CORE_INT; -- The Variable FPP_TO_CORE_INT is affected into FPP_TO_CORE

begin

-- Komponent Instanzierung mit Verdrahtung

U : Lane
port map (
S_FPP_CLK_IN,

S_FPP_FROM_CORE, -- j
S_DATA_IN, -- k
S_FPP_SEC_EN, -- b
S_FPP_TURN_SEL, -- c
S_FPP_CORE_SEL, -- d
S_FPP_REGP_BYP, -- e
S_FPP_SOURCE_SEL, -- f
S_FPP_REGN_BYP, -- g
S_FPP_PRI_EN, -- h
S_Primary_Port, -- i
S_Secondary_Port, -- a
S_DATA_OUT,
S_FPP_TO_CORE_INT
);


processClock : process
begin

S_FPP_CLK_IN <= '0';
wait for 10 ns;
S_FPP_CLK_IN <= '1';
wait for 10 ns;

end process processClock;

Stimuli : process
begin

S_FPP_FROM_CORE <= '0'; -- j
S_DATA_IN <= '0'; -- k
S_FPP_SEC_EN <= '0'; -- b
S_FPP_TURN_SEL <= '0'; -- c
S_FPP_CORE_SEL <= '0'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h
S_Primary_Port <= ''; -- i
S_Secondary_Port <= '0'; -- a

wait until S_FPP_CLK_IN <= '1';

S_FPP_FROM_CORE <= '-'; -- j
S_DATA_IN <= '-'; -- k
S_FPP_SEC_EN <= '1'; -- b
S_FPP_TURN_SEL <= '-'; -- c
S_FPP_CORE_SEL <= '1'; -- d
S_FPP_REGP_BYP <= '0'; -- e
S_FPP_SOURCE_SEL <= '0'; -- f
S_FPP_REGN_BYP <= '0'; -- g
S_FPP_PRI_EN <= '0'; -- h

--wait until S_FPP_CLK_IN <= '1';

S_Primary_Port <= '0';
wait until S_FPP_CLK_IN <= '0';

S_Primary_Port <= '1';
wait until S_FPP_CLK_IN <= '1';


end process Stimuli;

end archPrimToSecTest;

is there anyway to sent you the file?
Click to expand...

I don't want you to send me the file so I can debug your code. I want
you to look at the simulation results and understand what you see. I
will help you understand if you tell me what you don't understand or ask
questions.

--

Rick
 
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