Guest
Hi,
VHDL-illiterate here. I'm trying to hook up a xilinx logic probe in legacy VHDL code and am getting a complaint from the compiler that the expression length of the signal i'm feeding to the port doesn't match the expected size.
ila_inst: entity work.ila(rtl)
port map
(
clk => CLOCK,
probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0')
.....
According to the compiler (modelsim), the zero-fill i'm sending to the probe0 port has a expression length of only 9 bits and thus doesn't match the port size. I believe the expression as written should be defining 21 bits of 0's?
Anybody have an idea what I am missing?
Cheers,
Stephen
VHDL-illiterate here. I'm trying to hook up a xilinx logic probe in legacy VHDL code and am getting a complaint from the compiler that the expression length of the signal i'm feeding to the port doesn't match the expected size.
ila_inst: entity work.ila(rtl)
port map
(
clk => CLOCK,
probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0')
.....
According to the compiler (modelsim), the zero-fill i'm sending to the probe0 port has a expression length of only 9 bits and thus doesn't match the port size. I believe the expression as written should be defining 21 bits of 0's?
Anybody have an idea what I am missing?
Cheers,
Stephen