Guest
I have created a register file that holds 4 32 bit registers.Now i would like to check whether the first 3 bits of the first register(CTL) is 1 and then check if the 1st bit of 2nd register is 1 .If so the BC_en bit should go high.....which is not happening....can anyone please see the code below and help me?
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std_UNSIGNED.ALL;
entity cntrregFile is
port
(
input : in std_logic_vector (31 downto 0);
writeEnable : in std_logic;
clk : in std_logic;
readregSel : in std_logic_vector (2 downto 0);
writeregSel : in std_logic_vector (2 downto 0);
readEnable : in std_logic;
output : out std_logic_vector (31 downto 0);
bc_en : out std_logic
);
end cntrregFile;
architecture behavioral of cntrregFile is
type registerFile is array(0 to 3) of std_logic_vector(31 downto 0);
signal registers : registerFile;
signal CTL : std_logic_vector(31 downto 0);
signal BC_CTL : std_logic_vector(31 downto 0);
signal BC_FIFO_CTL : std_logic_vector(31 downto 0);
signal ENCDEC_CTL : std_logic_vector(31 downto 0);
begin
process (clk,writeregSel,writeEnable,readregSel,readEnable) is
begin
if (rising_edge(clk) and writeEnable='1' ) then
if ( writeregSel="000") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="001") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="010") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="011") then
registers (to_integer(writeregSel)) <= input ;
end if;
elsif (rising_edge(clk) and readEnable='1') then
if (readregSel="000") then
CTL <= registers(to_integer(readregSel));
output <= CTL;
elsif(readregSel="001") then
BC_CTL <= registers(to_integer(readregSel));
output<= BC_CTL;
elsif(readregSel="010") then
BC_FIFO_CTL <= registers(to_integer(readregSel));
output<= BC_FIFO_CTL;
elsif(readregSel="011") then
ENCDEC_CTL <= registers(to_integer(readregSel));
output<=ENCDEC_CTL ;
end if;
end if;
end process;
process (clk,CTL,BC_CTL) is
begin
if (CTL(0)= '1') and (CTL(1)='1') and
(CTL(2)='0') and (CTL(3)='0')then
if (BC_CTL(0) ='1') then
bc_en<= '1';
else
bc_en<='0';
end if;
end if;
end process;
end behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std_UNSIGNED.ALL;
entity cntrregFile is
port
(
input : in std_logic_vector (31 downto 0);
writeEnable : in std_logic;
clk : in std_logic;
readregSel : in std_logic_vector (2 downto 0);
writeregSel : in std_logic_vector (2 downto 0);
readEnable : in std_logic;
output : out std_logic_vector (31 downto 0);
bc_en : out std_logic
);
end cntrregFile;
architecture behavioral of cntrregFile is
type registerFile is array(0 to 3) of std_logic_vector(31 downto 0);
signal registers : registerFile;
signal CTL : std_logic_vector(31 downto 0);
signal BC_CTL : std_logic_vector(31 downto 0);
signal BC_FIFO_CTL : std_logic_vector(31 downto 0);
signal ENCDEC_CTL : std_logic_vector(31 downto 0);
begin
process (clk,writeregSel,writeEnable,readregSel,readEnable) is
begin
if (rising_edge(clk) and writeEnable='1' ) then
if ( writeregSel="000") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="001") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="010") then
registers (to_integer(writeregSel)) <= input ;
elsif ( writeregSel="011") then
registers (to_integer(writeregSel)) <= input ;
end if;
elsif (rising_edge(clk) and readEnable='1') then
if (readregSel="000") then
CTL <= registers(to_integer(readregSel));
output <= CTL;
elsif(readregSel="001") then
BC_CTL <= registers(to_integer(readregSel));
output<= BC_CTL;
elsif(readregSel="010") then
BC_FIFO_CTL <= registers(to_integer(readregSel));
output<= BC_FIFO_CTL;
elsif(readregSel="011") then
ENCDEC_CTL <= registers(to_integer(readregSel));
output<=ENCDEC_CTL ;
end if;
end if;
end process;
process (clk,CTL,BC_CTL) is
begin
if (CTL(0)= '1') and (CTL(1)='1') and
(CTL(2)='0') and (CTL(3)='0')then
if (BC_CTL(0) ='1') then
bc_en<= '1';
else
bc_en<='0';
end if;
end if;
end process;
end behavioral;