A
Adam Wysocki
Guest
Hi,
I started learning VHDL from the book "The Designer's Guide To VHDL"
(third edition) and I'm trying to make my first steps in it.
One of the exercises at the end of the first chapter asks to write an
entity declaration and a behavioral architecture body of a simple
multiplexer. Two inputs ('a' and 'b'), one selection input ('sel') and one
output, 'z', becoming 'a' if sel is 0, or 'b' if sel is 1.
I wrote the following code:
#v+
entity mux2 is
port (a, b, sel: in bit; z: out bit);
end entity mux2;
architecture mux2_behav of mux2 is begin
mux2: process is begin
if sel then
z <= b after 5ns;
else
z <= a after 5ns;
end if;
end process mux2;
end architecture mux2_behav;
#v-
(without test bench yet) and now I wanted to simulate it (I'm not sure if
it's possible without writing a test bench, but at least I want to have a
semantically correct architecture body).
Debian's apt-cache finds two simulators:
fauhdlc - experimental VHDL compiler and interpreter
freehdl - VHDL simulator for Linux
Unfortunately, gvhdl (freehdl's frontend) says that:
#v+
$ gvhdl ch1-10.vhdl
gvhdl: FreeHDL root path is '/usr'.
gvhdl: executing '/usr/bin/freehdl-v2cc -m ch1-10._main_.cc -L
/usr/share/freehdl/lib -o ch1-10.cc ch1-10.vhdl'
ch1-10.vhdl: in mux2(mux2_behav):
ch1-10.vhdl:7: sel does not match required type BOOLEAN, its type could be:
/usr/share/freehdl/lib/std/standard.vhdl:6: BIT
v2cc: ch1-10.vhdl: 1 errors
gvhdl: Compilation failed!
Died at /usr/bin/gvhdl line 211.
#v-
fauhdl doesn't recognize '5ns' symbol:
#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:8: Symbol '5ns' undefined.
ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined.
#v-
and after commenting it out says something similar to gvhdl:
#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:7: Type error for <sel>.
#v-
I understand that the statement "if sel then" is invalid for 'sel' being
a bit type, and not a boolean type.
This leads to my questions:
1. What am I doing wrong? Is it illegal to compare bits this way, or is it
legal only since a certain VHDL language version? The book says that it's
legal, but examples from the book fail with similar messages.
2. I don't know the VHDL version simulated by these two simulators, and if
they support VHDL-2008 or not. I read that comments /* ... */ are illegal
in VHDL versions prior to 2008, so I tried them in these simulators and
they complained, so I guess they support an older VHDL version.
I don't see any option to switch them to the 2008 version.
3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.
Thank you!
--
[ Adam Wysocki :: Warsaw, Poland ]
[ Email: a@b a=grp b=chmurka.net ]
[ Web: http://www.chmurka.net/ ]
I started learning VHDL from the book "The Designer's Guide To VHDL"
(third edition) and I'm trying to make my first steps in it.
One of the exercises at the end of the first chapter asks to write an
entity declaration and a behavioral architecture body of a simple
multiplexer. Two inputs ('a' and 'b'), one selection input ('sel') and one
output, 'z', becoming 'a' if sel is 0, or 'b' if sel is 1.
I wrote the following code:
#v+
entity mux2 is
port (a, b, sel: in bit; z: out bit);
end entity mux2;
architecture mux2_behav of mux2 is begin
mux2: process is begin
if sel then
z <= b after 5ns;
else
z <= a after 5ns;
end if;
end process mux2;
end architecture mux2_behav;
#v-
(without test bench yet) and now I wanted to simulate it (I'm not sure if
it's possible without writing a test bench, but at least I want to have a
semantically correct architecture body).
Debian's apt-cache finds two simulators:
fauhdlc - experimental VHDL compiler and interpreter
freehdl - VHDL simulator for Linux
Unfortunately, gvhdl (freehdl's frontend) says that:
#v+
$ gvhdl ch1-10.vhdl
gvhdl: FreeHDL root path is '/usr'.
gvhdl: executing '/usr/bin/freehdl-v2cc -m ch1-10._main_.cc -L
/usr/share/freehdl/lib -o ch1-10.cc ch1-10.vhdl'
ch1-10.vhdl: in mux2(mux2_behav):
ch1-10.vhdl:7: sel does not match required type BOOLEAN, its type could be:
/usr/share/freehdl/lib/std/standard.vhdl:6: BIT
v2cc: ch1-10.vhdl: 1 errors
gvhdl: Compilation failed!
Died at /usr/bin/gvhdl line 211.
#v-
fauhdl doesn't recognize '5ns' symbol:
#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:8: Symbol '5ns' undefined.
ERROR> ch1-10.vhdl:10: Symbol '5ns' undefined.
#v-
and after commenting it out says something similar to gvhdl:
#v+
$ fauhdlc ch1-10.vhdl
ERROR> ch1-10.vhdl:7: Type error for <sel>.
#v-
I understand that the statement "if sel then" is invalid for 'sel' being
a bit type, and not a boolean type.
This leads to my questions:
1. What am I doing wrong? Is it illegal to compare bits this way, or is it
legal only since a certain VHDL language version? The book says that it's
legal, but examples from the book fail with similar messages.
2. I don't know the VHDL version simulated by these two simulators, and if
they support VHDL-2008 or not. I read that comments /* ... */ are illegal
in VHDL versions prior to 2008, so I tried them in these simulators and
they complained, so I guess they support an older VHDL version.
I don't see any option to switch them to the 2008 version.
3. What simulators do you use or recommend? I prefer Linux ones (it would
be much easier for me), but if there are no reasonable ones, I can use
Windows ones as well. I want them only to test and simulate my code
snippets during learning. My final goal is to be able to make models
suitable for synthesis and upload into CPLD and FPGA devices.
Thank you!
--
[ Adam Wysocki :: Warsaw, Poland ]
[ Email: a@b a=grp b=chmurka.net ]
[ Web: http://www.chmurka.net/ ]