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3 bus arbiter verilog code
E
EML
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There is, unusually, an SO Q/A that addresses the \'why\' (https://stackoverflow.com/a/33504420/785194).
Basically, it\'s just historic confusion. If you go back to the early pre-IEEE LRMs it\'s obvious that a \'reg\' really was meant to be a register, and the concept of \'continuously driving\' wasn\'t well understood. This wasn\'t really rationalised until SV.
Basically, it\'s just historic confusion. If you go back to the early pre-IEEE LRMs it\'s obvious that a \'reg\' really was meant to be a register, and the concept of \'continuously driving\' wasn\'t well understood. This wasn\'t really rationalised until SV.
A
anuj.ranalonglastt@gmail.com
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On Monday, May 13, 2002 at 10:01:24 AM UTC+5:30, Chuck Benz wrote:
Hi, I need 64b/66b or 128b/130b implementation.
Can you please help.
For anyone interested, I have completed an 8b/10b implementation,
per Widmer and Franaszek (IBM JRD, Sep \'83). I\'ve posted it
at http://asics.chuckbenz.com.
You can use it quite freely, I only ask that you keep my copyright
header notice intact, even if you change the module name, or merge
it into your verilog code, or even if you translate it to VHDL
(shouldn\'t be hard). It\'s coded as a combinational block, so you
would add your own flop external to each block to latch disparity.
Logic designers might find a few other interesting things at my site,
and I hope to continue to add useful stuff - please feel free to offer
any feedback.
\\chuck
Chuck Benz
ASIC and FPGA design
newsbenz@chuckbenz.com
Hi, I need 64b/66b or 128b/130b implementation.
Can you please help.
R
Rick C
Guest
On Thursday, May 28, 2020 at 11:44:26 PM UTC-4, anuj.ran...@gmail.com wrote:
No, sorry.
--
Rick C.
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On Monday, May 13, 2002 at 10:01:24 AM UTC+5:30, Chuck Benz wrote:
For anyone interested, I have completed an 8b/10b implementation,
per Widmer and Franaszek (IBM JRD, Sep \'83). I\'ve posted it
at http://asics.chuckbenz.com.
You can use it quite freely, I only ask that you keep my copyright
header notice intact, even if you change the module name, or merge
it into your verilog code, or even if you translate it to VHDL
(shouldn\'t be hard). It\'s coded as a combinational block, so you
would add your own flop external to each block to latch disparity.
Logic designers might find a few other interesting things at my site,
and I hope to continue to add useful stuff - please feel free to offer
any feedback.
\\chuck
Chuck Benz
ASIC and FPGA design
newsbenz@chuckbenz.com
Hi, I need 64b/66b or 128b/130b implementation.
Can you please help.
No, sorry.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
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Thanks a lot, the hex file was included
in the work and I included the altera_sym_ver library as well but the output was always zero, finally it worked by changing the dictory to full path in my rom.v file.
in the work and I included the altera_sym_ver library as well but the output was always zero, finally it worked by changing the dictory to full path in my rom.v file.
S
server
Guest
On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
I\'m having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.
Hi everybody,
Does anyone could help me ?
I\'m currently trying to simulate a JK flip-flop Verilog-netlisted from
a schematic. And as Q is equal to x at the beginning, it always stays
at x...
So i need to initialize Q, but as it is an output it doesn \'t work,
even if i put it as an inout.
Could you give me some tips ?
Thanks by advance,
Alex
I\'m having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.
R
Rick C
Guest
On Friday, June 12, 2020 at 1:30:52 PM UTC-4, paslar...@gmail.com wrote:
Isn\'t that what initial blocks are for?
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On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
Hi everybody,
Does anyone could help me ?
I\'m currently trying to simulate a JK flip-flop Verilog-netlisted from
a schematic. And as Q is equal to x at the beginning, it always stays
at x...
So i need to initialize Q, but as it is an output it doesn \'t work,
even if i put it as an inout.
Could you give me some tips ?
Thanks by advance,
Alex
I\'m having the same problem in simulation if anyone know how to initialize the output Q at first time please tell us.
Isn\'t that what initial blocks are for?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
T
TJ Edmister
Guest
On Fri, 12 Jun 2020 13:30:49 -0400, <paslarerfan1@gmail.com> wrote:
Can you not use something like this?
initial q = 0;
Using Icarus verilog, I\'ve also been a bit frustrated by getting x\'s
everywhere. It seems that it will even give you a result of \'x\' in cases
where I would expect a real answer, like \'x\' AND 0, or \'x\' multiplied by
0. It would be nice if the simulator could be directed to automatically
make all registers zero, or fill them with random data, instead of me
having to manually specify it. However I could not find such an option in
the documentation.
On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
Hi everybody,
Does anyone could help me ?
I\'m currently trying to simulate a JK flip-flop Verilog-netlisted from
a schematic. And as Q is equal to x at the beginning, it always stays
at x...
So i need to initialize Q, but as it is an output it doesn \'t work,
even if i put it as an inout.
Could you give me some tips ?
Thanks by advance,
Alex
I\'m having the same problem in simulation if anyone know how to
initialize the output Q at first time please tell us.
Can you not use something like this?
initial q = 0;
Using Icarus verilog, I\'ve also been a bit frustrated by getting x\'s
everywhere. It seems that it will even give you a result of \'x\' in cases
where I would expect a real answer, like \'x\' AND 0, or \'x\' multiplied by
0. It would be nice if the simulator could be directed to automatically
make all registers zero, or fill them with random data, instead of me
having to manually specify it. However I could not find such an option in
the documentation.
R
Rick C
Guest
On Saturday, June 13, 2020 at 9:40:04 AM UTC-4, TJ Edmister wrote:
Initialization is not always a good idea unless your circuit will also provide initialization. But then your simulator should simulate logic functions properly. In VHDL anything anded with \'0\' is \'0\'. Are you sure that\'s not the same in Verilog? It would be very hard to get rid of the various non-logic states otherwise.
--
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On Fri, 12 Jun 2020 13:30:49 -0400, <paslarerfan1@gmail.com> wrote:
On Thursday, 28 March 2002 15:15:20 UTC+4:30, Alex wrote:
Hi everybody,
Does anyone could help me ?
I\'m currently trying to simulate a JK flip-flop Verilog-netlisted from
a schematic. And as Q is equal to x at the beginning, it always stays
at x...
So i need to initialize Q, but as it is an output it doesn \'t work,
even if i put it as an inout.
Could you give me some tips ?
Thanks by advance,
Alex
I\'m having the same problem in simulation if anyone know how to
initialize the output Q at first time please tell us.
Can you not use something like this?
initial q = 0;
Using Icarus verilog, I\'ve also been a bit frustrated by getting x\'s
everywhere. It seems that it will even give you a result of \'x\' in cases
where I would expect a real answer, like \'x\' AND 0, or \'x\' multiplied by
0. It would be nice if the simulator could be directed to automatically
make all registers zero, or fill them with random data, instead of me
having to manually specify it. However I could not find such an option in
the documentation.
Initialization is not always a good idea unless your circuit will also provide initialization. But then your simulator should simulate logic functions properly. In VHDL anything anded with \'0\' is \'0\'. Are you sure that\'s not the same in Verilog? It would be very hard to get rid of the various non-logic states otherwise.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209