Verilog programing query

I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions.
However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem?
Thanks

 

[rickman]

On 10/29/2015 8:29 AM, mahmedqureshi.maq@gmail.com wrote:

I am new to verilog programming. I have a assignment in which we are asked to make a 32 bit, 64 deep register file and store in it a set of 32 bit instructions.
However, these instruction are going to be instantiated in the test bench and not in the module. I have so far been unable to store these instructions in my register. Any ideas about how i may solve this problem?
Thanks

I'm not sure why you are asking how to write Verilog code in a VHDL
group. But to answer your question I suspect your professor wants you
to use arrays to implement the register file. Then you simply need to
initialize them to the instruction values.

--

Rick