UVM for VHDL

[HT-Lab]

For those who haven't seen it:

http://bitvis.no/resources/presentations/uvvm/

Looks promising and IMHO hugely important for the VHDL community (even
if you don't need it).

With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to
tackle complex verification jobs.

Regards,
Hans
www.ht-lab.com

 

onsdag 28. januar 2015 11.28.48 UTC+1 skrev HT-Lab fřlgende:

For those who haven't seen it:

http://bitvis.no/resources/presentations/uvvm/

Looks promising and IMHO hugely important for the VHDL community (even
if you don't need it).

With UVVM/OS-VVM/OVL/PSL and VHDL2008 I think we have a good tool set to
tackle complex verification jobs.

Regards,
Hans
www.ht-lab.com

Thanks Hans, for the nice feedback.
We plan to do the UVVM release in Q2 (May?) with a beta release in March.
We will present an introduction to UVVM at FPGA-forum in February, and probably publish the presentation not long after that. This will show what we will implement in the first version that is focused on making a good verification component system with a structured distribution of commands from the sequencer to the verification components. This will allow both direct commands and local sequencers - and an easily understandable way of controlling the test cases. After that we will continue with more advanced features.

Best regards
Espen
www.bitvis.no