use STD_LOGIC_UNSIGNED with NUMERIC_STD

[N.]

Hello,

I'm trying to port a very old design that had formerly used the deprecated STD_LOGIC_ARITH library with the new NUMERIC_STD library.

The old design has a substantial amount of unsigned additions of the following format :

c_slv <= a_slv + b_slv;

or

c_slv <= a_slv + 10;


I realize I should probably go through all of the code and recast it all to "unsigned" to make it play nice with numeric_std, but was curious if it was still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUMERIC_STD. As far as I can tell, it doesn't look like the overloaded functions will conflict at all.


PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUMERIC_STD_UNSIGNED is out.

Thanks.

 

[Jim Lewis]

std_logic_unsigned will work fine with Numeric_std.

Actually for a little humor, there are conflicts between std_logic_arith and std_logic_unsigned which cause ambiguity that do not exist in numeric_std.. Hence, not only does it work with numeric_std, it works better with numeric_std than with std_logic_arith.

My rule for RTL is that if it is math, it should be in either type signed or unsigned.

I also try to keep a pragmatic rule for updates and do not change old code unless it uses type unsigned or signed as a port or something internal to it is changing and there value to switching to the numeric_std package - ie: this block is going to be around for quite some time in the future.

 

[N.]

On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote:

std_logic_unsigned will work fine with Numeric_std.

Actually for a little humor, there are conflicts between std_logic_arith and std_logic_unsigned which cause ambiguity that do not exist in numeric_std. Hence, not only does it work with numeric_std, it works better with numeric_std than with std_logic_arith.

My rule for RTL is that if it is math, it should be in either type signed or unsigned.

I also try to keep a pragmatic rule for updates and do not change old code unless it uses type unsigned or signed as a port or something internal to it is changing and there value to switching to the numeric_std package - ie: this block is going to be around for quite some time in the future.

Thanks Jim.

My design's ports are still set at std_logic and std_logic_vector, mainly due to the fact that the numerous cores I'm using generated by CoreGen are still using this convention. I will think about converting the math related ports to unsigned/signed for future designs.

BTW, I enjoyed your write-up on VHDL math tricks Very good reference.

 

[Andy]

On Thursday, September 3, 2015 at 8:20:39 AM UTC-5, Jim Lewis wrote:

> My rule for RTL is that if it is math, it should be in either type signed or unsigned.

Agreed, and I would add the IEEE VHDL fixed point types (ufixed or sfixed) and floating point type (float) to that list.

Andy

 

On Thursday, September 3, 2015 at 2:29:19 AM UTC+3, N. wrote:

Hello,

I'm trying to port a very old design that had formerly used the deprecated STD_LOGIC_ARITH library with the new NUMERIC_STD library.

The old design has a substantial amount of unsigned additions of the following format :

c_slv <= a_slv + b_slv;

or

c_slv <= a_slv + 10;

....
use ieee.STD_LOGIC_UNSIGNED."+";
....
learn_cnti <=
--load
mem_do(43 downto 40) when fsm_ps(c_loc_read1) = '1' else
--increment
std_logic_vector(unsigned(learn_cntq) + "0001") when
fsm_ps(c_loc_ave0) = '1'
else learn_cntq;
....
For more info see vhdl examples at
http://bknpk.ddns.net/my_web/MiscellaneousHW/MiscellaneousHW.html

I realize I should probably go through all of the code and recast it all to "unsigned" to make it play nice with numeric_std, but was curious if it was still acceptable in industry to use STD_LOGIC_UNSIGNED library with NUMERIC_STD. As far as I can tell, it doesn't look like the overloaded functions will conflict at all.


PS: VHDL-2008 doesn't play nice with my current tools (ISE), so using NUMERIC_STD_UNSIGNED is out.

Thanks.