I
Igor Orlovsky
Guest
Hi all!
Please give me a clue on optimizing complex design in BuildGates.
I have a design with large number of multiply instantiated
subdesigns. Each subdesign is also hierarchical and contains
several inistances of another subdesign. I want to perform
pre-layout synthesis and optimization, so would like
to keep repeated submodules as single Verilog modules
without uniquifying them. However, I should set some timing
constants inside the repeated submodules along with set multicycle
paths. BuildGates prohibited such references and needs to make
all the mentioned instances unique (do_uniquify_instantiate) as
referenced objects are not-unique from its point of view.
If such, I have to uniquify top -level instances (and clone
repeated modules in design) and also uniquify repeated
internal instances inside each top-level instances.
All this need more memory and future optimization work.
For example, if I have 10 instances of subdesign A at the top
level I have to
do_uniquely_instantiate -hier {i1 i2 i3 i4 i5 i6 i7 i8 i9 i10}
If each A design contain 3 instances of B design, I also have
to uniquify each 3 instances in each ten subdesigns
to refer their internal variable
do_uniquely_instantiate -hier {i1/i1 i1/i2 i1/i3}
do_uniquely_instantiate -hier {i2/i1 i2/i2 i2/i3}
......
do_uniquely_instantiate -hier {i10/i1 i10/i2 i10/i3}
Anyway, now I have much large design, needs more memory
and optimization of each new subdesign. This process is
more close to physical optimization, and need more computer
resources than considered at pre-layout optimization stage.
In fact, this kind of designs could be well-optimized
when applying top-level constraints ONLY and don't need
any uniquifying. However as soon as I need to refer any internal
object (instance/pin/path) inside repeated instanced I meet
the above problems.
Is there any approach, avoiding uniquifying in BuildGates?
I am wonder, if such problem exists in Synopsys Design Compler
too?
Thanks
Igor Orlovsky
--
Igor Orlovsky
ASIC team leader
Topcon Positioning Systems CIS, LLC
E-mail: IOrlovsky@topcon.com
Please give me a clue on optimizing complex design in BuildGates.
I have a design with large number of multiply instantiated
subdesigns. Each subdesign is also hierarchical and contains
several inistances of another subdesign. I want to perform
pre-layout synthesis and optimization, so would like
to keep repeated submodules as single Verilog modules
without uniquifying them. However, I should set some timing
constants inside the repeated submodules along with set multicycle
paths. BuildGates prohibited such references and needs to make
all the mentioned instances unique (do_uniquify_instantiate) as
referenced objects are not-unique from its point of view.
If such, I have to uniquify top -level instances (and clone
repeated modules in design) and also uniquify repeated
internal instances inside each top-level instances.
All this need more memory and future optimization work.
For example, if I have 10 instances of subdesign A at the top
level I have to
do_uniquely_instantiate -hier {i1 i2 i3 i4 i5 i6 i7 i8 i9 i10}
If each A design contain 3 instances of B design, I also have
to uniquify each 3 instances in each ten subdesigns
to refer their internal variable
do_uniquely_instantiate -hier {i1/i1 i1/i2 i1/i3}
do_uniquely_instantiate -hier {i2/i1 i2/i2 i2/i3}
......
do_uniquely_instantiate -hier {i10/i1 i10/i2 i10/i3}
Anyway, now I have much large design, needs more memory
and optimization of each new subdesign. This process is
more close to physical optimization, and need more computer
resources than considered at pre-layout optimization stage.
In fact, this kind of designs could be well-optimized
when applying top-level constraints ONLY and don't need
any uniquifying. However as soon as I need to refer any internal
object (instance/pin/path) inside repeated instanced I meet
the above problems.
Is there any approach, avoiding uniquifying in BuildGates?
I am wonder, if such problem exists in Synopsys Design Compler
too?
Thanks
Igor Orlovsky
--
Igor Orlovsky
ASIC team leader
Topcon Positioning Systems CIS, LLC
E-mail: IOrlovsky@topcon.com