there is a problem with if statement please help me

[rama hareesh]

here my code is

i am doing lift control based on spartan 3e for my 4th year student

here there a problem with if condition


here my problem will present if srx='1'



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity lift is
Port ( b0 : in STD_LOGIC;
clk: in std_logic;
b1 : in STD_LOGIC;
b2 : in STD_LOGIC;
srx : in STD_LOGIC;
s0 : out STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC;
m1 : out STD_LOGIC;
m0 : out STD_LOGIC);

end lift;

architecture Behavioral of lift is
type STATE_TYPE is (f0, f1, f2, mup1,mup2,mdown1, mdown0);
signal nes:state_type;
begin
process(b0,b1,b2,srx,clk)
begin
if(clk' event and clk='1') then

case nes is

--Ground floor
when f0=>
s0<='1';
s1<='0';
s2<='0';

if srx='1' then
--m1<='0';
--m0<='0';
if b1='1' then
s0<='0';
-- s1<='1';
-- s2<='0';
--m1<='1';
--m0<='0';
nes<=mup1;
elsif b2='1' then
s0<='0';
s1<='0';
s2<='1';
--m1<='1' after 5ns;
--m0<='0';
nes<=mup2;
else nes<=f0;
end if;
end if;
-- first floor up
when f1=>
if srx='1' then
-- m1<='0';
-- m0<='0';
if b0='1' then
s0<='1';
s1<='0';
s2<='0';
m1<='0' after 5ns;
m0<='1';
nes<=mdown0;
elsif b2='1' then
s0<='0';
s1<='0';
s2<='1';
--m1<='1' after 5ns;
--m0<='0';
nes<=mup2;
else nes<=f1;
end if;
end if;

-- sencond floor

when f2=>
if srx ='1' then
-- m1<='0';
-- m0<='0';
if b0='1' then
s0<='1';
s1<='0';
s2<='0';
--m1<='0' after 5ns;
--m0<='1';
nes<=mdown0;
elsif b1='1' then
s0<='0';
s1<='1';
s2<='0';
--m1<='0' after 5ns;
--m0<='1';
nes<=mdown1;
else
nes<=f2;
end if;
end if;

when mup1=>
m1<='1';
m0<='0';
s0<='0';
s1<='1';
s2<='0';
if srx='0' then
m1<='0';
m0<='0';
nes<=f1;
else
nes<=mup1;
end if;
when mup2=>
m1<='1';
m0<='0';
nes<=f2;

when mdown1=>
m1<='0';
m0<='1';
nes<=f1;

when mdown0=>
m1<='0';
m0<='1';
nes<=f0;
end case;

end if;

end process;

end Behavioral;

 

[Nicolas Matringe]

Le 29/03/2015 10:42, rama hareesh a ĂŠcrit :

here my code is
i am doing lift control based on spartan 3e for my 4th year student
here there a problem with if condition
here my problem will present if srx='1'

Ok, can you now describe the actual problem ?

Nicolas


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[colin_toogood@yahoo.com]

A couple of simple things to begin with.

1) You say this code is going in a spartan 3e.
THE VERY FIRST THING THAT YOU HAVE TO DO IS UNDERSTAND WHAT AN FPGA IS.
Then you will understand that there is no "after 5ns" magic. If you have tried to synthesize yet you will find a "I have ignored this" message in the log files.

2) You have to understand what a process is.
Then you will replace your process line with "process(clk)", unless you have cut some asynchronous stuff but I doubt it.

Colin