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TCL Error...

  • Thread starter Kr. Sheelvardhan Banty
  • Start date
K

Kr. Sheelvardhan Banty

Guest
When I try to open a new project in Modelsim It gives me this error:-

** Error: (vlib-35) Failed to create directory \"C:/intelFPGA/20.1/work\".
Permission denied. (errno = EACCES)
child process exited abnormally
while executing
\"exec $vlib $worklib\"
(procedure \"Project::create\" line 45)
invoked from within
\"Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)\"
(procedure \"Project::applyCreate\" line 3)
invoked from within
\"Project::applyCreate .pcd\"
invoked from within
\".pcd.bb.button0 invoke\"
(\"uplevel\" body line 1)
invoked from within
\"uplevel #0 [list $w invoke]\"
(procedure \"tk::ButtonUp\" line 24)
invoked from within
\"tk::ButtonUp .pcd.bb.button0\"
(command bound to event)
 
H

HT-Lab

Guest
Looks like you have hit some read/write permissions. Try creating a
simple design outside of the installation tree:

vlib work
vmap work work
vlog/vcom xx

I would also strongly advice not to use Modelsim projects, a .do or .tcl
file is all you need and far more flexible. If you are worried about
compile time you can use vmake+make.

Good luck,
Hans
www.ht-lab.com


On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote:
When I try to open a new project in Modelsim It gives me this error:-

** Error: (vlib-35) Failed to create directory \"C:/intelFPGA/20.1/work\".
Permission denied. (errno = EACCES)
child process exited abnormally
while executing
\"exec $vlib $worklib\"
(procedure \"Project::create\" line 45)
invoked from within
\"Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)\"
(procedure \"Project::applyCreate\" line 3)
invoked from within
\"Project::applyCreate .pcd\"
invoked from within
\".pcd.bb.button0 invoke\"
(\"uplevel\" body line 1)
invoked from within
\"uplevel #0 [list $w invoke]\"
(procedure \"tk::ButtonUp\" line 24)
invoked from within
\"tk::ButtonUp .pcd.bb.button0\"
(command bound to event)
 
K

Kr. Sheelvardhan Banty

Guest
On Thursday, 17 September 2020 at 13:18:47 UTC+5:30, HT-Lab wrote:
Looks like you have hit some read/write permissions. Try creating a
simple design outside of the installation tree:

vlib work
vmap work work
vlog/vcom xx

I would also strongly advice not to use Modelsim projects, a .do or .tcl
file is all you need and far more flexible. If you are worried about
compile time you can use vmake+make.

Good luck,
Hans
www.ht-lab.com
On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote:
When I try to open a new project in Modelsim It gives me this error:-

** Error: (vlib-35) Failed to create directory \"C:/intelFPGA/20.1/work\".
Permission denied. (errno = EACCES)
child process exited abnormally
while executing
\"exec $vlib $worklib\"
(procedure \"Project::create\" line 45)
invoked from within
\"Project::create $Project(dlg_proj_location) $Project(CurProj_NewName) $Project(dlg_proj_libname) $Project(dlg_initial_ini) $Project(dlg_ini_copy)\"
(procedure \"Project::applyCreate\" line 3)
invoked from within
\"Project::applyCreate .pcd\"
invoked from within
\".pcd.bb.button0 invoke\"
(\"uplevel\" body line 1)
invoked from within
\"uplevel #0 [list $w invoke]\"
(procedure \"tk::ButtonUp\" line 24)
invoked from within
\"tk::ButtonUp .pcd.bb.button0\"
(command bound to event)
I always get the message :-
Transcript : permission denied
 
H

HT-Lab

Guest
On 17/09/2020 11:22, Kr. Sheelvardhan Banty wrote:
On Thursday, 17 September 2020 at 13:18:47 UTC+5:30, HT-Lab wrote:
Looks like you have hit some read/write permissions. Try creating a
simple design outside of the installation tree:

vlib work
vmap work work
vlog/vcom xx

I would also strongly advice not to use Modelsim projects, a .do or .tcl
file is all you need and far more flexible. If you are worried about
compile time you can use vmake+make.

Good luck,
Hans
www.ht-lab.com
On 17/09/2020 08:22, Kr. Sheelvardhan Banty wrote:
When I try to open a new project in Modelsim It gives me this error:-

...
I always get the message :-
Transcript : permission denied
The transcript output is written to a text file to the same work
directory Modelsim is complaining about.

Have you checked the permissions for the \"C:/intelFPGA/20.1/work\"
directory? have you tried another directory?

Hans
www.ht-lab.com
 
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