J
Jacko
Guest
Hi all
http://nibz.googlecode.com VHDL microprocessor. Now I was wondering if
non process sensitivity variable latching is built into any tools for
lower switching/lower power operation?
I was also wondering if any tools had an auto wait state fit
calculator. That is to say a design simulation, where completion to
the synchronous clock was calculated for correct T(su and hold) and a
wait state clock generator was automade, and inserted so that a higher
clock rate could be achived, for the simpler evaluation paths to work
faster. Much better than inserting pipeline registers with there T(p
delay), and locking of a specific synchronization speed. Yes you may
get more speed from a pipeline by parallel execution, but you also get
much worse power efficiency, and a larger sythesis. If a two stage
pipeline device can get double the speed at best, and two non-
pipelined devices are smaller together, and can be sped up by wait
states at a higher clock, then what benefits?
As to process technology, if the synth tool of choice makes caltech
mask files, or such, then building in a new technology layer may be of
benefit. Take a regular CMOS FET and add a parallel one on the bottom
with a higher channel doping (so it don't switch on) it does however
store (via drain/gate feedback) an anti phase charge which can be
injected/stole from the conduction channel. This reduces miller effect
increasing Ft. When it comes to series wired FETs in gates, then some
miller bottom gate wiring to most active drain (output) needs to
happen for best speed. Please number the bottom poly-silicon and
channel mask field layers (it may need more?)
Well that's all for now folks
cheer jacko
Simon Jackson, BEng. (Elec/Electron)
Creative Technologist
K Ring Technologies
E: jackokring -at- gmail.com
http://nibz.googlecode.com VHDL microprocessor. Now I was wondering if
non process sensitivity variable latching is built into any tools for
lower switching/lower power operation?
I was also wondering if any tools had an auto wait state fit
calculator. That is to say a design simulation, where completion to
the synchronous clock was calculated for correct T(su and hold) and a
wait state clock generator was automade, and inserted so that a higher
clock rate could be achived, for the simpler evaluation paths to work
faster. Much better than inserting pipeline registers with there T(p
delay), and locking of a specific synchronization speed. Yes you may
get more speed from a pipeline by parallel execution, but you also get
much worse power efficiency, and a larger sythesis. If a two stage
pipeline device can get double the speed at best, and two non-
pipelined devices are smaller together, and can be sped up by wait
states at a higher clock, then what benefits?
As to process technology, if the synth tool of choice makes caltech
mask files, or such, then building in a new technology layer may be of
benefit. Take a regular CMOS FET and add a parallel one on the bottom
with a higher channel doping (so it don't switch on) it does however
store (via drain/gate feedback) an anti phase charge which can be
injected/stole from the conduction channel. This reduces miller effect
increasing Ft. When it comes to series wired FETs in gates, then some
miller bottom gate wiring to most active drain (output) needs to
happen for best speed. Please number the bottom poly-silicon and
channel mask field layers (it may need more?)
Well that's all for now folks
cheer jacko
Simon Jackson, BEng. (Elec/Electron)
Creative Technologist
K Ring Technologies
E: jackokring -at- gmail.com