Systemverilog static variable for derived class issue?

[Huaxin]

Check out the following code:

class env_class;
//all kinds of interfaces, variables, functions etc
endclass

class test_base;
static env_class env;
function new();
endfunction
endclass

class test_spec1 extends test_base;
function new();
super.new();
endfunction

function foo();
//Some action using stuff defined in env_class env
endfunction
endclass

class test_spec2 extends test_base;//A different kind of test
function new();
super.new();
endfunction

function foo();
//Some action using stuff defined in env_class env
endfunction
endclass

//Top module
module test_top;

env_class env;
test_spec1 test1;
test_spec2 test2;

initial begin
env = new();
test_base::env = env;
test1 = new();
test2 = new();

test1.foo();
test2.foo();
end
endmodule

when running things in Modelsim, the compiler said "Class or package
"test_base" not found"...According to my understanding of "static",
when it's in the base class(in this case test_base), it's shared by
all derived class(in this case test_spec1 and test_spec2), without an
instance of the base class. Is that right? Please tell me what should
I do to make it work. Thanks!