std_ulogic_vector and std_logic_vector

[fl]

Hi,
I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of
ABCD. If it is std_logic_vector, there are more cases to consider.

I know general input would have type std_logic_vector.

My question is whether there is a simple way to convert std_logic_vector to
std_ulogic_vector?

Thanks,



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Number_of_Ones is
port (
--- mapped 3=a, 2=b, 1=c, 0=d
abcd : in std_ulogic_vector(3 downto 0);
-- mapped x=2, y=1, z=0
xyz : out std_ulogic_vector(2 downto 0);
);
end entity;

architecture any of Number_of_Ones is
begin

process (abcd) is
begin
case abcd of
--ABCD|XYZ
when "0000" => xyz <= "000";
when "0001" => xyz <= "001";
when "0010" => xyz <= "001";
when "0011" => xyz <= "010";
when "0100" => xyz <= "011";
when "0101" => xyz <= "010";
when "0110" => xyz <= "010";
when "0111" => xyz <= "011";
when "1000" => xyz <= "001";
when "1001" => xyz <= "010";
when "1010" => xyz <= "010";
when "1011" => xyz <= "011";
when "1100" => xyz <= "010";
when "1101" => xyz <= "011";
when "1110" => xyz <= "011";
when "1111" => xyz <= "100";
end case;
end process;

 

[KJ]

On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote:

Hi,
I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of
ABCD. If it is std_logic_vector, there are more cases to consider.

That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector.

My question is whether there is a simple way to convert std_logic_vector to
std_ulogic_vector?

signal my_sulv: std_ulogic_vector(...);
signal my_slv: std_logic_vector(...);
....
my_sulv <= std_ulogic_vector(my_slv);
my_slv <= std_logic_vector(my_sulv);

Kevin Jennings

 

[rickman]

On 9/25/2015 11:20 AM, fl wrote:

Hi,
I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of
ABCD. If it is std_logic_vector, there are more cases to consider.

I believe std_ulogic_vector and std_logic_vector have the same value
range. The difference is the result when signals are driven by multiple
drivers. If you want to preclude the possibilities of inferring
multiple drivers you can use std_ulogic_vector and errors will be
flagged when multiple drivers are on the sane signal. With
std_logic_vector the value goes to U or X, but no error is flagged in
simulation. I'm not sure how synthesis handles multiple drivers on
std_ulogic_vector signals.

I know general input would have type std_logic_vector.

My question is whether there is a simple way to convert std_logic_vector to
std_ulogic_vector?

Yeah....

std_logic_signal <= std_ulogic_signal;

--- or ---

xyz <= some expression of (std_logic'std_ulogic_signal);

I believe these two logic types are completely interchangeable.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Number_of_Ones is
port (
--- mapped 3=a, 2=b, 1=c, 0=d
abcd : in std_ulogic_vector(3 downto 0);
-- mapped x=2, y=1, z=0
xyz : out std_ulogic_vector(2 downto 0);
);
end entity;

architecture any of Number_of_Ones is
begin

process (abcd) is
begin
case abcd of
--ABCD|XYZ
when "0000" => xyz <= "000";
when "0001" => xyz <= "001";
when "0010" => xyz <= "001";
when "0011" => xyz <= "010";
when "0100" => xyz <= "011";
when "0101" => xyz <= "010";
when "0110" => xyz <= "010";
when "0111" => xyz <= "011";
when "1000" => xyz <= "001";
when "1001" => xyz <= "010";
when "1010" => xyz <= "010";
when "1011" => xyz <= "011";
when "1100" => xyz <= "010";
when "1101" => xyz <= "011";
when "1110" => xyz <= "011";
when "1111" => xyz <= "100";
end case;
end process;

I think this also has the error for when "0100".

--

Rick

 

[rickman]

On 9/25/2015 2:24 PM, KJ wrote:

On Friday, September 25, 2015 at 11:20:29 AM UTC-4, fl wrote:
Hi,
I notice that below code uses 'std_ulogic_vector'. It can write 16 cases of
ABCD. If it is std_logic_vector, there are more cases to consider.


That's not true. There are exactly the same number of cases. I think you may be confusing with bit_vector.

My question is whether there is a simple way to convert std_logic_vector to
std_ulogic_vector?


signal my_sulv: std_ulogic_vector(...);
signal my_slv: std_logic_vector(...);
....
my_sulv <= std_ulogic_vector(my_slv);
my_slv <= std_logic_vector(my_sulv);

Those would be conversion functions and I don't think they exist for
those types. Those types are "closely related" and require no
conversion or type specification to convert. In essence they can be
mixed as if they were the same type.

Am I wrong?

--

Rick

 

[KJ]

On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote:

Those would be conversion functions and I don't think they exist for
those types. Those types are "closely related" and require no
conversion or type specification to convert. In essence they can be
mixed as if they were the same type.

Am I wrong?

Like any good question, the answer is 'It depends'.

For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wrong, the two are not closely related types. They are separate types so you need a type conversion to go from one to the other. With VHDL-2008, you are correct that no type conversion is required.

For std_logic and std_ulogic you never needed a conversion function because std_logic is defined to be a subtype of std_ulogic. This is the way that std_logic_vector should have been defined in the first place...VHDL-2008 corrected that (finally).

Kevin Jennings

 

[rickman]

On 9/26/2015 12:11 AM, KJ wrote:

On Friday, September 25, 2015 at 5:18:19 PM UTC-4, rickman wrote:
Those would be conversion functions and I don't think they exist for
those types. Those types are "closely related" and require no
conversion or type specification to convert. In essence they can be
mixed as if they were the same type.

Am I wrong?


Like any good question, the answer is 'It depends'.

For std_logic_vector and std_ulogic_vector, prior to VHDL-2008, you were wrong, the two are not closely related types. They are separate types so you need a type conversion to go from one to the other. With VHDL-2008, you are correct that no type conversion is required.

For std_logic and std_ulogic you never needed a conversion function because std_logic is defined to be a subtype of std_ulogic. This is the way that std_logic_vector should have been defined in the first place...VHDL-2008 corrected that (finally).

I'll have to take your word for it. I don't have any of my books with
me and I'm too lazy to look this up on the Internet.

--

Rick