G
George
Guest
Hello!
I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like
to make a SPI interface. So now I need a VHDL description of an 8 bit
parallel-in serial-out shift register with MSB shifting out first. So
far I haven't had any luck so I am asking you for help. I thank you in
advance for your efforts.
Best regards
George Mercury
I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like
to make a SPI interface. So now I need a VHDL description of an 8 bit
parallel-in serial-out shift register with MSB shifting out first. So
far I haven't had any luck so I am asking you for help. I thank you in
advance for your efforts.
Best regards
George Mercury