Selecting between two clock signals

David Lamb · Aug 28, 2003

Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode of
operation, I want to switch between two different clock signals. I will
never switch on the fly though. Can I use a mux in front of the clock_in
input? I'm afraid it might glitch.
Thanks
David

Marten · Aug 28, 2003

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...

Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode of
operation, I want to switch between two different clock signals. I will
never switch on the fly though. Can I use a mux in front of the clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead you
to xl24_20.pdf, a neat little circuit that hopefully will ease your worries

Keep in mind that whatever you put in the clock path will affect the setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

Andrew Paule · Aug 28, 2003

this is dependant on what chip he is using - is this only a xilinx
newsgroup?

Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...

Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode of
operation, I want to switch between two different clock signals. I will
never switch on the fly though. Can I use a mux in front of the clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead you
to xl24_20.pdf, a neat little circuit that hopefully will ease your worries

Keep in mind that whatever you put in the clock path will affect the setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

John_H · Aug 28, 2003

Fortunately there are things that come out of Xilinx that are applicable to
all digital logic.
That XCELL article is one of them if you chose to look.

"Andrew Paule" <lsboogy@qwest.net> wrote in message
news:a2t3b.29$qq3.17593@news.uswest.net...

this is dependant on what chip he is using - is this only a xilinx
newsgroup?

Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...

Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode
of
operation, I want to switch between two different clock signals. I will
never switch on the fly though. Can I use a mux in front of the
clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead
you
to xl24_20.pdf, a neat little circuit that hopefully will ease your
worries

Keep in mind that whatever you put in the clock path will affect the
setup
and hold time requirements for the particular component.

Take care,

Marten

Peter Alfke · Aug 28, 2003

Click at
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

This circuit allows totally asynchronous selection between two clock sources.
But remember: both clock must be wiggling (however slowly). You cannot
use this circuit to enable/disable a clock, which is actually a far
simpler problem.
The BUFGMUX in Virtex is not quite this clever, it has a set-up time
requirement on the S control input. :-(
Glad that someone found this old tidbit useful...
Peter Alfke
=============================
Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...
Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode of
operation, I want to switch between two different clock signals. I will
never switch on the fly though. Can I use a mux in front of the clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead you
to xl24_20.pdf, a neat little circuit that hopefully will ease your worries

Keep in mind that whatever you put in the clock path will affect the setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

Uwe Bonnes · Aug 29, 2003

Peter Alfke <peter@xilinx.com> wrote:
: Click at
: http://www.xilinx.com/xcell/xl24/xl24_20.pdf

: This circuit allows totally asynchronous selection between two clock sources.
: But remember: both clock must be wiggling (however slowly). You cannot
: use this circuit to enable/disable a clock, which is actually a far
: simpler problem.
: The BUFGMUX in Virtex is not quite this clever, it has a set-up time
: requirement on the S control input. :-(

Peter,

what happens if this setup time is violated? Will the BUFGMUX stall (no more
output clock until some reset), will it produce a runt ( some clock pulse
smaller than any of both input clocks) or will it switch clocks only
delayed? I didn't find anything in the datasheet.

Nye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Peter Alfke · Aug 29, 2003

Uwe Bonnes wrote:

Peter,

what happens if this setup time is violated? Will the BUFGMUX stall (no more
output clock until some reset), will it produce a runt ( some clock pulse
smaller than any of both input clocks) or will it switch clocks only
delayed? I didn't find anything in the datasheet.

I don't know off-hand,. Will look into this when I am back from the
European FPL2003 conference, i.e. Sept 8.
Peter Alfke

Nye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Austin Lesea · Sep 2, 2003

Uwe,

If the setup is violated, there may be a runt pulse. It will not stall, as soon as
the next set of control signals comes along, it will operate normally again.

Austin

Uwe Bonnes wrote:

Peter Alfke <peter@xilinx.com> wrote:
: Click at
: http://www.xilinx.com/xcell/xl24/xl24_20.pdf

: This circuit allows totally asynchronous selection between two clock sources.
: But remember: both clock must be wiggling (however slowly). You cannot
: use this circuit to enable/disable a clock, which is actually a far
: simpler problem.
: The BUFGMUX in Virtex is not quite this clever, it has a set-up time
: requirement on the S control input. :-(

Peter,

what happens if this setup time is violated? Will the BUFGMUX stall (no more
output clock until some reset), will it produce a runt ( some clock pulse
smaller than any of both input clocks) or will it switch clocks only
delayed? I didn't find anything in the datasheet.

Nye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Austin Lesea · Sep 2, 2003

Jay,

Better in a relative sense: it does not have a setup time requirement (Peter's
circuit).

But, Peter's circuit does not match all delays, and keep the skew to 0 as part
of the DCM feedback loop, either.

Austin

Jay wrote:

Peter,

So you mean this circuit is better than the BUFGMUX?

"Peter Alfke" <peter@xilinx.com> ??????:3F4E7B2D.CFBD1D0D@xilinx.com...
Click at
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

This circuit allows totally asynchronous selection between two clock
sources.
But remember: both clock must be wiggling (however slowly). You cannot
use this circuit to enable/disable a clock, which is actually a far
simpler problem.
The BUFGMUX in Virtex is not quite this clever, it has a set-up time
requirement on the S control input. :-(
Glad that someone found this old tidbit useful...
Peter Alfke
=============================
Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...
Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode
of
operation, I want to switch between two different clock signals. I
will
never switch on the fly though. Can I use a mux in front of the
clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead
you
to xl24_20.pdf, a neat little circuit that hopefully will ease your
worries

Keep in mind that whatever you put in the clock path will affect the
setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

David Lamb · Sep 3, 2003

Hi,
I used your circuit to switch between the two clocks. However, when I
synthetise in Xilinx ISE 5.2, I get the following warning:

(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.

I don't really understand what it means. I guess I need to tell ISE that the
output of the circuit is a clock, but I don't know how...

Thanks a lot
David

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F4E7B2D.CFBD1D0D@xilinx.com...

Click at
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

This circuit allows totally asynchronous selection between two clock
sources.
But remember: both clock must be wiggling (however slowly). You cannot
use this circuit to enable/disable a clock, which is actually a far
simpler problem.
The BUFGMUX in Virtex is not quite this clever, it has a set-up time
requirement on the S control input. :-(
Glad that someone found this old tidbit useful...
Peter Alfke
=============================
Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...
Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode
of
operation, I want to switch between two different clock signals. I
will
never switch on the fly though. Can I use a mux in front of the
clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead
you
to xl24_20.pdf, a neat little circuit that hopefully will ease your
worries

Keep in mind that whatever you put in the clock path will affect the
setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

Austin Lesea · Sep 3, 2003

David,

It simply means the tool is not smart enough to figure out what you are doing,
and since you have jumped off of a global clock resource, and passed through
logic on regular interconnect, skew and delay are no longer being kept track of
(it doesn't know where the clock comes from/goes to).

So, yes I think you have to tell it what is what, but since I am not a
software/synthesis guru, I can not tell you how to do that. Perhaps someone
else can,

Austin

David Lamb wrote:

Hi,
I used your circuit to switch between the two clocks. However, when I
synthetise in Xilinx ISE 5.2, I get the following warning:

(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.

I don't really understand what it means. I guess I need to tell ISE that the
output of the circuit is a clock, but I don't know how...

Thanks a lot
David

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3F4E7B2D.CFBD1D0D@xilinx.com...
Click at
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

This circuit allows totally asynchronous selection between two clock
sources.
But remember: both clock must be wiggling (however slowly). You cannot
use this circuit to enable/disable a clock, which is actually a far
simpler problem.
The BUFGMUX in Virtex is not quite this clever, it has a set-up time
requirement on the S control input. :-(
Glad that someone found this old tidbit useful...
Peter Alfke
=============================
Marten wrote:

"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bilfne$sel$1@home.itg.ti.com...
Hi all,
I have a vhdl component with a "clock_in" input. Depending on the mode
of
operation, I want to switch between two different clock signals. I
will
never switch on the fly though. Can I use a mux in front of the
clock_in
input? I'm afraid it might glitch.
Thanks
David

David,

Do a query for 'clock sources' in the category 'XCELL Journals' on the
Xilinx web site. This will provide you with a link called 'XCELL 24 -
Trouble-Free Switching Between Clocks (Q1 97)', which, in turn will lead
you
to xl24_20.pdf, a neat little circuit that hopefully will ease your
worries

Keep in mind that whatever you put in the clock path will affect the
setup
and hold time requirements for the particular component.

Take care,

Marten

] remove the obvious to repy by e-mail [

Selecting between two clock signals

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