saif format

[Vandana]

Hi

1. Im trying to generate the switching activity of my design using the
SAIF format in dc-shell.

So far, I have been able to generate the switching activity of the top
level design using the rtl2saif commands and then in the simulation
with back annoatation.

The problem is that I get the switching activity of only the top-level
design. Is there a way to get the switching activity of every cell in
the netlist? I want the switching activity of the verilog file that
is written after synthesis.
Is there a way to do this?

2. Can somebody please point out the usage of the saif_map command?

Thanks,
----------------

Steps that I am following:
In DC

analyze
elaborate
link
compile
rtl2saif -output x_fw.saif -design my_deisgn
lib2saif -output "my.saif" "90 tech library".db
----------------------
use vcs to simulate the testbench
---------------------
In test bench Im using the pli calls
read_lib_saif("my.saif")
$read_rtl_saif("x_fw.saif, mydesign.instance)
$set_gate_level_monitoring("on")
set_toggle_region("mydesign.instance")
$toggle_start
.....
...
$toggle_stop
$toggle_report("x_bw.saif, 1.0e-9, mydesign.instance)
$finish
---------------------------
x-bw.saif contains switcihing activity of only the ports of the
design.

With the above only the inputs & outputs are monitored for switching
activity.
How can I get the switching activity of all the cells in the design?

Thanks for your time & help