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Please comrades I want to find out when a SET states and a RESET state are obtained in an RS flip flop.
The Net has been confusing me with conflicting facts but l know this learned and honored group will settle it for me as you always do
is the state determined by the S (SET) input or the Q output? Is the criteria the same for both the NOR and NAND gates?
Thank you
The Net has been confusing me with conflicting facts but l know this learned and honored group will settle it for me as you always do
is the state determined by the S (SET) input or the Q output? Is the criteria the same for both the NOR and NAND gates?
Thank you