J
JohnSmith
Guest
Hi,
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM :
t_array :=("10001","10010","10100","10101","10110","11000","11001","11010",
"11011","11100","11101","11110","11110","11111","11111","11111",
"11111","11111","11111","11110","11110","11101","11100","11011",
"11010","11001","11000","10110","10101","10100","10010","10001",
"01111","01110","01100","01011","01010","01000","00111","00110",
"00101","00100","00011","00010","00010","00001","00001","00001",
"00001","00001","00001","00010","00010","00011","00100","00101",
"00110","00111","01000","01010","01011","01100","01110","01111");
Thanks
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM :
t_array :=("10001","10010","10100","10101","10110","11000","11001","11010",
"11011","11100","11101","11110","11110","11111","11111","11111",
"11111","11111","11111","11110","11110","11101","11100","11011",
"11010","11001","11000","10110","10101","10100","10010","10001",
"01111","01110","01100","01011","01010","01000","00111","00110",
"00101","00100","00011","00010","00010","00001","00001","00001",
"00001","00001","00001","00010","00010","00011","00100","00101",
"00110","00111","01000","01010","01011","01100","01110","01111");
Thanks