RLOC specification

  • Thread starter Martin Euredjian
  • Start date
M

Martin Euredjian

Guest
How do I specify the use of the F or G LUT in a slice?
Can I?
Does it matter? Why?
How do you reduce wasted resources if you can't specify this in an RPM?


The following code:

//synthesis attribute RLOC of BIT[0].SRL is X0Y0
//synthesis attribute RLOC of BIT[1].SRL is X0Y0
//synthesis attribute RLOC of BIT[2].SRL is X0Y1
//synthesis attribute RLOC of BIT[3].SRL is X0Y1
....etc.

places SRLC16's from a Verilog "generate" block, but I can't seem to control
which of the two LUT's is used for pairs of bits.

The module in question generates a SRLC16-based delay block of variable (at
instantiation) word size and delay. This is a building block for a FIR
filter and I'd like to control placement as tightly as possible. Instead of
getting a nice upward or downward sequential distribution, the above
produces a sequence like this (assuming an 8-bit word):

BIT[6].SRL (top-most slice SRL)
BIT[7].SRL
BIT[4].SRL
BIT[5].SRL
BIT[2].SRL
BIT[3].SRL
BIT[0].SRL
BIT[1].SRL (bottom-most slice SRL)

When, what I really want is:

BIT[7].SRL (top-most slice SRL)
BIT[6].SRL
BIT[5].SRL
BIT[4].SRL
BIT[3].SRL
BIT[2].SRL
BIT[1].SRL
BIT[0].SRL (bottom-most slice SRL)

Thanks,


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
 
You have to add a BEL constraint to control which half of the slice pieces end
up in. There are six strings that are valid values for the BEL. I define a
couple of constant arrays to make them addressable with an index to make it more
amenable to being used with generates. In many cases you can get away without
the BELs, because for non-arithmetic logic it usually doesn't matter which half
of the slice the logic goes into. WHere it does matter is if you are using the
BX, BY inputs or carry chains. There are 3 pairs of BEL values, one for the
LUT, one for the flip-flop and one for the XOR_CY. The MUXCY's don't need it
because the position is inferred by the connectivity.

type bel_lut_type is array (0 to 1) of string (1 to 1);
type bel_ff_type is array (0 to 1) of string (1 to 3);
type bel_xor_type is array (0 to 1) of string (1 to 4);
constant bel_lut:bel_lut_type:= ("F","G");
constant bel_ff:bel_ff_type:= ("FFX","FFY");
constant bel_xor:bel_xor_type:=("XORF","XORG");

attribute BEL of U1:label is bel_lut(i mod 2);
attribute BEL of U3:label is bel_xor(i mod 2);
attribute BEL of U4:label is bel_ff(i mod 2);
attribute BEL of U5:label is bel_ff(i mod 2);
attribute RLOC of U1 : label is rloc_str;
attribute RLOC of U2 : label is rloc_str;
attribute RLOC of U3 : label is rloc_str;
attribute RLOC of U4 : label is rloc_str;
attribute RLOC of U5 : label is rloc_str;

Martin Euredjian wrote:

How do I specify the use of the F or G LUT in a slice?
Can I?
Does it matter? Why?
How do you reduce wasted resources if you can't specify this in an RPM?

The following code:

//synthesis attribute RLOC of BIT[0].SRL is X0Y0
//synthesis attribute RLOC of BIT[1].SRL is X0Y0
//synthesis attribute RLOC of BIT[2].SRL is X0Y1
//synthesis attribute RLOC of BIT[3].SRL is X0Y1
...etc.

places SRLC16's from a Verilog "generate" block, but I can't seem to control
which of the two LUT's is used for pairs of bits.

The module in question generates a SRLC16-based delay block of variable (at
instantiation) word size and delay. This is a building block for a FIR
filter and I'd like to control placement as tightly as possible. Instead of
getting a nice upward or downward sequential distribution, the above
produces a sequence like this (assuming an 8-bit word):

BIT[6].SRL (top-most slice SRL)
BIT[7].SRL
BIT[4].SRL
BIT[5].SRL
BIT[2].SRL
BIT[3].SRL
BIT[0].SRL
BIT[1].SRL (bottom-most slice SRL)

When, what I really want is:

BIT[7].SRL (top-most slice SRL)
BIT[6].SRL
BIT[5].SRL
BIT[4].SRL
BIT[3].SRL
BIT[2].SRL
BIT[1].SRL
BIT[0].SRL (bottom-most slice SRL)

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Thanks Ray, that did it.

Note to Xilinx:
Page 184 of the ISE6.1i Constraints Guide seems to have a typo: "FFT" should
be "FFY"


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"



"Ray Andraka" <ray@andraka.com> wrote in message
news:3F8220F4.920E48D3@andraka.com...
You have to add a BEL constraint to control which half of the slice pieces
end
up in. There are six strings that are valid values for the BEL. I define
a
couple of constant arrays to make them addressable with an index to make
it more
amenable to being used with generates. In many cases you can get away
without
the BELs, because for non-arithmetic logic it usually doesn't matter which
half
of the slice the logic goes into. WHere it does matter is if you are
using the
BX, BY inputs or carry chains. There are 3 pairs of BEL values, one for
the
LUT, one for the flip-flop and one for the XOR_CY. The MUXCY's don't need
it
because the position is inferred by the connectivity.

type bel_lut_type is array (0 to 1) of string (1 to 1);
type bel_ff_type is array (0 to 1) of string (1 to 3);
type bel_xor_type is array (0 to 1) of string (1 to 4);
constant bel_lut:bel_lut_type:= ("F","G");
constant bel_ff:bel_ff_type:= ("FFX","FFY");
constant bel_xor:bel_xor_type:=("XORF","XORG");

attribute BEL of U1:label is bel_lut(i mod 2);
attribute BEL of U3:label is bel_xor(i mod 2);
attribute BEL of U4:label is bel_ff(i mod 2);
attribute BEL of U5:label is bel_ff(i mod 2);
attribute RLOC of U1 : label is rloc_str;
attribute RLOC of U2 : label is rloc_str;
attribute RLOC of U3 : label is rloc_str;
attribute RLOC of U4 : label is rloc_str;
attribute RLOC of U5 : label is rloc_str;

Martin Euredjian wrote:

How do I specify the use of the F or G LUT in a slice?
Can I?
Does it matter? Why?
How do you reduce wasted resources if you can't specify this in an RPM?

The following code:

//synthesis attribute RLOC of BIT[0].SRL is X0Y0
//synthesis attribute RLOC of BIT[1].SRL is X0Y0
//synthesis attribute RLOC of BIT[2].SRL is X0Y1
//synthesis attribute RLOC of BIT[3].SRL is X0Y1
...etc.

places SRLC16's from a Verilog "generate" block, but I can't seem to
control
which of the two LUT's is used for pairs of bits.

The module in question generates a SRLC16-based delay block of variable
(at
instantiation) word size and delay. This is a building block for a FIR
filter and I'd like to control placement as tightly as possible.
Instead of
getting a nice upward or downward sequential distribution, the above
produces a sequence like this (assuming an 8-bit word):

BIT[6].SRL (top-most slice SRL)
BIT[7].SRL
BIT[4].SRL
BIT[5].SRL
BIT[2].SRL
BIT[3].SRL
BIT[0].SRL
BIT[1].SRL (bottom-most slice SRL)

When, what I really want is:

BIT[7].SRL (top-most slice SRL)
BIT[6].SRL
BIT[5].SRL
BIT[4].SRL
BIT[3].SRL
BIT[2].SRL
BIT[1].SRL
BIT[0].SRL (bottom-most slice SRL)

Thanks,

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top