Reverse ?? Operator...

[Rick C]

I\'m starting a new project so I need to come up the learning curve again. I always forget details of the language when I don\'t use it for some time.

I think I\'m not so much not remembering something that is in the language as it is I\'m thinking of something that\'s NOT in the language, but I wish it were. I\'m probably mixing my poor recollection of C with my poor recollection of VHDL.

VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn\'t in VHDL) it runs onto two lines. I also don\'t like the syntax which spreads the two alternatives to opposite ends of the statement.

The syntax I\'m remembering is something like

A <= condition ?? X : Y

I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it.

So someone tell me I\'m totally misremembering it. I\'ve dug the Internet and not found any gold. I\'m pretty sure I would have found it if it were there.

Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Mike Perkins]

On 08/09/2020 03:44:30, Rick C wrote:

I\'m starting a new project so I need to come up the learning curve again. I always forget details of the language when I don\'t use it for some time.

I think I\'m not so much not remembering something that is in the language as it is I\'m thinking of something that\'s NOT in the language, but I wish it were. I\'m probably mixing my poor recollection of C with my poor recollection of VHDL.

VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn\'t in VHDL) it runs onto two lines. I also don\'t like the syntax which spreads the two alternatives to opposite ends of the statement.

The syntax I\'m remembering is something like

A <= condition ?? X : Y

I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it.

So someone tell me I\'m totally misremembering it. I\'ve dug the Internet and not found any gold. I\'m pretty sure I would have found it if it were there.

Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function.

That works for C. I presume you\'re looking for something like this?

For VHDL
s <= waveform_1 when condition_1 else
waveform_2 when condition_2 else
...
waveform_n;

As per:
https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf

In a process it would be more usual to use an if statement

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Rick C]

On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:

On 08/09/2020 03:44:30, Rick C wrote:
I\'m starting a new project so I need to come up the learning curve again. I always forget details of the language when I don\'t use it for some time.

I think I\'m not so much not remembering something that is in the language as it is I\'m thinking of something that\'s NOT in the language, but I wish it were. I\'m probably mixing my poor recollection of C with my poor recollection of VHDL.

VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn\'t in VHDL) it runs onto two lines. I also don\'t like the syntax which spreads the two alternatives to opposite ends of the statement.

The syntax I\'m remembering is something like

A <= condition ?? X : Y

I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it.

So someone tell me I\'m totally misremembering it. I\'ve dug the Internet and not found any gold. I\'m pretty sure I would have found it if it were there.

Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function.

That works for C. I presume you\'re looking for something like this?

For VHDL
s <= waveform_1 when condition_1 else
waveform_2 when condition_2 else
...
waveform_n;

As per:
https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf

In a process it would be more usual to use an if statement

Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;

Called thusly:

Spkr_Blip <= b_to_sl(Button_Press(I) = Buttons_Past(I));

It just seems something like b_to_sl should/could be part of the language or a standard library. I noticed when I google searched on it, there was no shortage of others asking the same question.

The above test is checking for a change in the button state. The input is Buttons which is low true so Buttons_Past is low true while Button_Press is the debounced version and high true. I think I should add Buttons_ht, a high true version of the input signal and make everything from that point on high true to keep the logic easier to read.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[HT-Lab]

On 08/09/2020 14:35, Rick C wrote:

On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
...
VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

...
Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;

I hit exactly the same issue many years ago and a VHDL guru\'s called
Tricky (if I remember correctly) suggested to use simple functions. Like
most VHDL engineers I now have a package with lots of helper functions I
collected over the years. Here is a good site with lots of conversion
functions:

https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html

However, the reason for replying is that I also tried to use the ??
operator recently and failed to make it work, I had something like:

if (?? (OR slvarray(1 downto 0)) OR (a > b)) then..

however, to make it work you need extra brackets as in :

if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then..

Or to simplify, you need (??(non_boolean))

Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I
just added the brackets and moved on with life.....

I am sure somebody with more VHDL knowledge can explain why the extra
(non-obvious) brackets are required.

Hans
www.ht-lab.com

 

[Rick C]

On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote:

On 08/09/2020 14:35, Rick C wrote:
On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
..
VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

..
Yeah, I\'m trying to make this construct a simple one line piece of code.. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;


I hit exactly the same issue many years ago and a VHDL guru\'s called
Tricky (if I remember correctly) suggested to use simple functions. Like
most VHDL engineers I now have a package with lots of helper functions I
collected over the years. Here is a good site with lots of conversion
functions:

https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html

However, the reason for replying is that I also tried to use the ??
operator recently and failed to make it work, I had something like:

if (?? (OR slvarray(1 downto 0)) OR (a > b)) then..

however, to make it work you need extra brackets as in :

if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then..

Or to simplify, you need (??(non_boolean))

Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I
just added the brackets and moved on with life.....

I am sure somebody with more VHDL knowledge can explain why the extra
(non-obvious) brackets are required.

Hans
www.ht-lab.com

Can\'t say for sure, but likely it\'s a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight.

When I do my work I use a library or two, but this a many years collection of stuff, much of which is obsolete, but still is needed by some code, somewhere. I will need to start a project specific package at some point just like I\'m going to need to split the HDL into multiple files for multiple entities rather than putting them all together in one.

For now I\'m just focusing on getting some functionality going.

I\'m using the Lattice tools with ActiveHDL for simulation which I\'ve used many time. It seems to only work with files located in the source directory within the project. I can add a source file from outside of the project, but it gets copied into the project directory.

I don\'t want to have to use their project directory for the source files because they are essentially commingled with the other 5 billion trash files every design creates which I have no interest in backing up. Is there a way to tell it to work with the files in *MY* directory which is not in the project? I thought I knew how to do this, but I guess not. It\'s not easy to find info on this sort of thing. I did find one page that simply says, \"don\'t fight with the tools, the tools always win.\"



--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Charles Bailey]

On 2020-09-08 08:35, Rick C wrote:

On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
I\'m starting a new project so I need to come up the learning curve again. I always forget details of the language when I don\'t use it for some time.

I think I\'m not so much not remembering something that is in the language as it is I\'m thinking of something that\'s NOT in the language, but I wish it were. I\'m probably mixing my poor recollection of C with my poor recollection of VHDL.

VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn\'t in VHDL) it runs onto two lines. I also don\'t like the syntax which spreads the two alternatives to opposite ends of the statement.

The syntax I\'m remembering is something like

A <= condition ?? X : Y

I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it.

So someone tell me I\'m totally misremembering it. I\'ve dug the Internet and not found any gold. I\'m pretty sure I would have found it if it were there.

Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function.

That works for C. I presume you\'re looking for something like this?

For VHDL
s <= waveform_1 when condition_1 else
waveform_2 when condition_2 else
...
waveform_n;

As per:
https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf

In a process it would be more usual to use an if statement

Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;

Called thusly:

Spkr_Blip <= b_to_sl(Button_Press(I) = Buttons_Past(I));

It just seems something like b_to_sl should/could be part of the language or a standard library. I noticed when I google searched on it, there was no shortage of others asking the same question.

The above test is checking for a change in the button state. The input is Buttons which is low true so Buttons_Past is low true while Button_Press is the debounced version and high true. I think I should add Buttons_ht, a high true version of the input signal and make everything from that point on high true to keep the logic easier to read.

VHDL2008 contains functions to do comparisons of std_logic, which would
normally return a Boolean result, but return a std_logic result.

From the 2008 IEEE std_logic_1164.vhdl package source file:
-- the following operations are predefined

-- function \"?=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?=\" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;

-- function \"?/=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?/=\" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;

-- function \"?<\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?<=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?>\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?>=\" (l, r : STD_ULOGIC) return STD_ULOGIC;

Charles Bailey

 

[Rick C]

On Thursday, September 10, 2020 at 12:39:42 AM UTC-4, Charles Bailey wrote:

On 2020-09-08 08:35, Rick C wrote:
On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
I\'m starting a new project so I need to come up the learning curve again. I always forget details of the language when I don\'t use it for some time.

I think I\'m not so much not remembering something that is in the language as it is I\'m thinking of something that\'s NOT in the language, but I wish it were. I\'m probably mixing my poor recollection of C with my poor recollection of VHDL.

VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

I can do what I want to do using when and else, but they tend to make the line more crowded, so if the expression is a bit wordy (what isn\'t in VHDL) it runs onto two lines. I also don\'t like the syntax which spreads the two alternatives to opposite ends of the statement.

The syntax I\'m remembering is something like

A <= condition ?? X : Y

I think this is the C construct. I just have this image in my mind of this being trotted out as a new VHDL feature, or something like it.

So someone tell me I\'m totally misremembering it. I\'ve dug the Internet and not found any gold. I\'m pretty sure I would have found it if it were there.

Or is there a conversion for boolean to std_logic? I seem to remember searching that the other day and finding nothing other than examples of your own conversion function.

That works for C. I presume you\'re looking for something like this?

For VHDL
s <= waveform_1 when condition_1 else
waveform_2 when condition_2 else
...
waveform_n;

As per:
https://www.ics.uci.edu/~alexv/154/VHDL-Cookbook.pdf

In a process it would be more usual to use an if statement

Yeah, I\'m trying to make this construct a simple one line piece of code.. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;

Called thusly:

Spkr_Blip <= b_to_sl(Button_Press(I) = Buttons_Past(I));

It just seems something like b_to_sl should/could be part of the language or a standard library. I noticed when I google searched on it, there was no shortage of others asking the same question.

The above test is checking for a change in the button state. The input is Buttons which is low true so Buttons_Past is low true while Button_Press is the debounced version and high true. I think I should add Buttons_ht, a high true version of the input signal and make everything from that point on high true to keep the logic easier to read.


VHDL2008 contains functions to do comparisons of std_logic, which would
normally return a Boolean result, but return a std_logic result.

From the 2008 IEEE std_logic_1164.vhdl package source file:
-- the following operations are predefined

-- function \"?=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?=\" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;

-- function \"?/=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?/=\" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;

-- function \"?<\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?<=\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?>\" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function \"?>=\" (l, r : STD_ULOGIC) return STD_ULOGIC;

Charles Bailey

That works in this case. I was comparing two bits of unsigned for being not alike and wasn\'t thinking I could just XNOR them. Geeze! The ?/= works as well. Thanks

It\'s been too long since I\'ve used this language.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[HT-Lab]

On 08/09/2020 19:03, Rick C wrote:

On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote:
On 08/09/2020 14:35, Rick C wrote:
On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
..
VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

..
Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;


I hit exactly the same issue many years ago and a VHDL guru\'s called
Tricky (if I remember correctly) suggested to use simple functions. Like
most VHDL engineers I now have a package with lots of helper functions I
collected over the years. Here is a good site with lots of conversion
functions:

https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html

However, the reason for replying is that I also tried to use the ??
operator recently and failed to make it work, I had something like:

if (?? (OR slvarray(1 downto 0)) OR (a > b)) then..

however, to make it work you need extra brackets as in :

if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then..

Or to simplify, you need (??(non_boolean))

Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I
just added the brackets and moved on with life.....

I am sure somebody with more VHDL knowledge can explain why the extra
(non-obvious) brackets are required.

Hans
www.ht-lab.com

Can\'t say for sure, but likely it\'s a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight.

I am not sure, from what I know ?? is just an overloaded function so
??() should be resolved before OR which has the lowest precedence,


Regards,
Hans.

 

[Rick C]

On Wednesday, September 16, 2020 at 3:04:59 AM UTC-4, HT-Lab wrote:

On 08/09/2020 19:03, Rick C wrote:
On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote:
On 08/09/2020 14:35, Rick C wrote:
On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
..
VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

..
Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;


I hit exactly the same issue many years ago and a VHDL guru\'s called
Tricky (if I remember correctly) suggested to use simple functions. Like
most VHDL engineers I now have a package with lots of helper functions I
collected over the years. Here is a good site with lots of conversion
functions:

https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html

However, the reason for replying is that I also tried to use the ??
operator recently and failed to make it work, I had something like:

if (?? (OR slvarray(1 downto 0)) OR (a > b)) then..

however, to make it work you need extra brackets as in :

if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then..

Or to simplify, you need (??(non_boolean))

Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I
just added the brackets and moved on with life.....

I am sure somebody with more VHDL knowledge can explain why the extra
(non-obvious) brackets are required.

Hans
www.ht-lab.com

Can\'t say for sure, but likely it\'s a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight.

I am not sure, from what I know ?? is just an overloaded function so
??() should be resolved before OR which has the lowest precedence,


Regards,
Hans.

I don\'t think being overloaded affects the priority. Why do you say OR is lower than ??... It\'s hard to find info on ?? for VHDL. I haven\'t seen it in any precedence lists.

Turns out ?? is hard to search on. In Google it is treated as nothing at all. Bing will return proper results on just ??, but not on VHDL ?? or even VHDL \"??\" . Go figure.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[HT-Lab]

On 16/09/2020 19:21, Rick C wrote:

On Wednesday, September 16, 2020 at 3:04:59 AM UTC-4, HT-Lab wrote:
On 08/09/2020 19:03, Rick C wrote:
On Tuesday, September 8, 2020 at 11:21:54 AM UTC-4, HT-Lab wrote:
On 08/09/2020 14:35, Rick C wrote:
On Tuesday, September 8, 2020 at 8:36:14 AM UTC-4, Mike Perkins wrote:
On 08/09/2020 03:44:30, Rick C wrote:
..
VHDL has a ?? operator that converts a std_logic or bit value to Boolean. It took me a while to realize I\'m looking for something that does the opposite, converts a Boolean to a std_logic value.

..
Yeah, I\'m trying to make this construct a simple one line piece of code. For the time being I\'ve created a function:

function b_to_sl (X : boolean) return std_logic is begin
if X then return \'1\'; else return \'0\'; end if; end b_to_sl;


I hit exactly the same issue many years ago and a VHDL guru\'s called
Tricky (if I remember correctly) suggested to use simple functions. Like
most VHDL engineers I now have a package with lots of helper functions I
collected over the years. Here is a good site with lots of conversion
functions:

https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html

However, the reason for replying is that I also tried to use the ??
operator recently and failed to make it work, I had something like:

if (?? (OR slvarray(1 downto 0)) OR (a > b)) then..

however, to make it work you need extra brackets as in :

if ((?? (OR slvarray(1 downto 0))) OR (a > b)) then..

Or to simplify, you need (??(non_boolean))

Apparently this is described in section 9.2.9 of the 1076-2008 LRM but I
just added the brackets and moved on with life.....

I am sure somebody with more VHDL knowledge can explain why the extra
(non-obvious) brackets are required.

Hans
www.ht-lab.com

Can\'t say for sure, but likely it\'s a matter of precedence. The second OR tries to operate on the boolean and the std_logic from the first OR before the ?? has had a chance to do its thing. The extra set of parenthesis set the order straight.

I am not sure, from what I know ?? is just an overloaded function so
??() should be resolved before OR which has the lowest precedence,


Regards,
Hans.

I don\'t think being overloaded affects the priority. Why do you say OR is lower than ??...

I didn\'t, I said ?? should be resolved before the OR.

I assumed ??(x) is similar to something like std2bool(x) in which case
\"std2bool(x) OR\" is the same as \"(std2bool(x)) OR\" but with the ?? this
is not the case.

It\'s hard to find info on ?? for VHDL. I haven\'t seen it in any
precedence lists.

Because it is an overloaded function (see std_logic_1164.vhd)

Turns out ?? is hard to search on. In Google it is treated as nothing at all. Bing will return proper results on just ??, but not on VHDL ?? or even VHDL \"??\" . Go figure.

Yes I had difficulties googling it as well and only found the Doulos
page, I suspect ?? is not widely used in the VHDL community.

Hans
www.ht-lab.com




>