register naming

[mnentwig]

Hello,

is there a special term for a register that is not required to preserve it
content longer than the next clock cycle?

What I'm looking for is the following construct

always @(posedge clk) begin
myReg <= b'x;

case (state)


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[glen herrmannsfeldt]

mnentwig <24789@embeddedrelated> wrote:

is there a special term for a register that is not required
to preserve its content longer than the next clock cycle?

What I'm looking for is the following construct

always @(posedge clk) begin
myReg <= b'x;

In days past, there was dynamic logic. Intel used it at least
through the 8086 and 8088, which gives them a minimum clock
frequency, otherwise the registers lose the data.

Besides the extra instrutions, the Z80 was built with static
logic, such that the clock could stop, or slow down to 1Hz,
useful for debugging.

I haven't followed them so close, but I believe that CCDs would
be considered dynamic logic. There also used to be dynamic shift
registers, up to about 512 bits in an 8 pin package. Again, you
have to keep shifting or the bits fade away.

I believe that you can write pass transistors in verilog, which,
along with the capacitance of an MOS gate (and wiring) would allow
generation of such dynamic logic. I don't believe that any FPGAs
allow for it, though.

-- glen