register naming

[mnentwig]

(web browser got trigger-happy with the previous post... trying again).

Is there a special term for a register that is never required to keep it
contents for longer than the next clock cycle?

I'm thinking about the following code:

always @(posedge clk) begin
myReg <= 1'bx
case (state)
123: myReg <= someValue
234: myReg <= someOtherValue
default: /* no assignment to myReg */
end

The background is that reuse of the resource is possible across differen
states.
Now how would I call such a register?

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[Mark Curry]

In article <6LydnaJSFucEclfPnZ2dnUVZ_jKdnZ2d@giganews.com>,
mnentwig <24789@embeddedrelated> wrote:

Is there a special term for a register that is never required to keep its
contents for longer than the next clock cycle?

I'm thinking about the following code:

always @(posedge clk) begin
myReg <= 1'bx
case (state)
123: myReg <= someValue
234: myReg <= someOtherValue
default: /* no assignment to myReg */
end

The background is that reuse of the resource is possible across different
states.
Now how would I call such a register?

Don't know of any specific name for such a register. It's still just a
register. Now, me I loathe to actually introduce X's into code as you've
done. (This goes against many coding suggestions). X's can mean many
things - your use of the 'X' is to tell the synthesis tool it's a don't
care, and can optimize accordingly. I'd just assign it to one of the
already decoded states (i.e. someValue, or SomeOtherValue), or just gate
the enable and not change the state at all, and not worry about
any other possible (real or imagined) optimizations.

Regards,

Mark

 

[Mark Curry]

In article <P-KdnbFyPLEVgVbPnZ2dnUVZ_rqdnZ2d@giganews.com>,
mnentwig <24789@embeddedrelated> wrote:

Thanks!

I'd consider the "X" merely a formalism. I don't want to promote it as a
coding style (discussion here:
http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf)
But if I have a pipelined algorithm where the sharing of resources is
clearly mapped out, the situation is fairly straightforward (it would look
like Tetris bricks on a spreadsheet).

What I'm looking into is resource sharing in an FPGA, a dual-port RAM and
MAC (and this is BTW a toy project, not work related)

"Transient" register didn't show up on Google, at least it seems to have no
other meaning. Maybe I'll use that.

Well, the register's not really transient, but it's definition changes
according to state correct?

Quite a while a ago I had something similar - some algorithm I'd designed
with the help of a spreadsheet. Something where the registers definitions
changed according to state. (It may have been an FFT, but I don't recall).

Anyway, the algorithm worked itself out in the spreadsheet, and I then
color-coded the "registers" along the time access to account for
every register in hardware. The color indicated the actual hardware
register, the position in the spreadsheet represented where it was
(statewise) in the algorithm. It was easy to visualize the
whole algorithm and how many registers it needed this way.

I ended up naming the register in the RTL the color of the cell
in the spreadsheet. Had some confusing conversations with my back
end folks. 'Uh Mark, we're having timing closure problems
between "Blue" and "Red"'... heh.

I've never needed anything like this since. Most of my designs
now are fully pipelined. And to tell the truth if I did need
something like it now, I'd probably just create the extra
registers with wild abandon, and let synthesis do with it what it may...

Regards,

Mark

 

[mnentwig]

Thanks!

I'd consider the "X" merely a formalism. I don't want to promote it as
coding style (discussion here
http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf)
But if I have a pipelined algorithm where the sharing of resources i
clearly mapped out, the situation is fairly straightforward (it would loo
like Tetris bricks on a spreadsheet).

What I'm looking into is resource sharing in an FPGA, a dual-port RAM an
MAC (and this is BTW a toy project, not work related)

"Transient" register didn't show up on Google, at least it seems to have n
other meaning. Maybe I'll use that.


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[mnentwig]

Well, the register's not really transient, but it's definition changes
according to state correct?

True... maybe there is a better word. Simply "shared" could do.

I think it's also not exactly encouraged by Verilog. It seems ver
difficult to code a shared register, until all the logic is in a singl
"always @(clk)" block. Virtual tristates are something I don't want t
touch, somehow I suspect it wouldn't help the design tool.

Cheers

Markus

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