Reducing verbosity in structural entity declaration

Hello,

I recently learnt that, since VHDL'93, components are not needed any more, and entities can be directly instantiated [0]. So that I can replace this architecture

--entity testent is
-- port ( CLK: in std_logic );
--end testent;

--architecture withcomponents of testent is
---component mycomp
---port ( CLK, D: in std_logic;
--- Q: out std_logic );
---end component;
---signal f2s: std_logic;
--begin
---MODA: mycomp port map ( CLK, open, f2s);
---MODB: mycomp port map ( CLK, f2s, open);
--end withcomponents;

with

--architecture withoutcomponents of testent is
---signal f2s: std_logic;
--begin
---MODA: entity work.mycomp port map ( CLK, open, f2s);
---MODB: entity work.mycomp port map ( CLK, f2s, open);
--end withoutcomponents;

On top of that, I would like to know whether VHDL supports any expression so that the declaration of the signal 'f2s' is not required. Something similar to:

--architecture direct of testent is
--begin
---MODA: entity work.mycomp port map ( CLK, open, MODB.D);
---MODB: entity work.mycomp port map ( CLK, MODA.Q, open);
--end direct;

Which from my point of view would be explained as: can VHDL understand the ports of an instantiated entity as if it was a record? I've tried it in ISE with no success, and I've found no similar examples, so I would say that it's not supported. However, I'd like to know your opinions, in case you think that such a feature makes sense, or to hear of alternatives to achieve a similar scheme.

I've found this message [1] sent to the VHDL-200X - DASC mailing list in Feb 2003, which is much ambitious than what I'm asking. However, since it is related, I'd like to be pointed to any later reference on it, if any.

----

Moreover, although I've presented a really simple example, I'd like to use such a feature inside generate environments. Thus, to achieve so, besides supporting such an expression, the label of the instantiation should provide references to each of the actually synthetized modules. A shift register, with such an implicit declarations, would be:

--architecture direct of testent is
--begin
---MODS: for k in 7 downto 0 generate
----case k generate
-----when 0 =>
------MODS(k): entity work.mycomp port map ( CLK, open, MODS(k+1).D);
-----when 7 =>
------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D);
-----when others =>
------MODS(k): entity work.mycomp port map ( CLK, MODS(k-1).Q, open);
----end generate;
---end generate;
--end direct;

or

--architecture direct of testent is
--begin
---MODS: for k in 7 downto 0 generate
----MODS(k): case k generate
-----when 0 =>
------entity work.mycomp port map ( CLK, open, MODS(k+1).D);
-----when 7 =>
------entity work.mycomp port map ( CLK, MODS(k-1).Q, MODS(k+1).D);
-----when others =>
------entity work.mycomp port map ( CLK, MODS(k-1).Q, open);
----end generate;
---end generate;
--end direct;

I'm quite sure that this is not supported neither in VHDL'93 nor in VHDL'08.. Nevertheless, to those of you who know the internals, does this feature(s) make any sense to you? Or is rather specific?

[0] http://www.sigasi.com/content/four-and-half-ways-write-vhdl-instantiations
[1] http://www.eda.org/vhdl-200x/hm/0040.html

 

As a bonus conceptual script, this is what I would expect to be nearly minimum verbosity while still maintaing VHDL syntax (with richer generate structures):

--architecture direct of testent is
--begin
---MODS: for k in 7 downto 0 generate
----MODS(k): entity work.mycomp port map ( CLK,
-----[case k generate when 0 => open; when others => MODS(k-1).Q; end generate;] ,
-----[case k generate when 7 => open; when others => MODS(k+1).D; end generate;] );
---end generate;
--end direct;

 

[KJ]

On Saturday, May 9, 2015 at 6:29:47 PM UTC-4, una...@gmail.com wrote:
You can't do exactly what you want since you're using 'MODS' both as the name of the instantiation as well as the name of a signal. However, you will need to define the record structure and make an array of it anyway so there will be just as much typing to do that, naming the signal uniquely isn't any time saver.

Kevin Jennings