I
Isaac
Guest
Hi Champs
Its Isaac after long time,,,,,,,,,,,,,,I am having problem reading out
values from SRAM in FPGA everytime I try to target SRAM I am getting
0. The code is given below . The check node and variable node
component's function is not mentioned here.
Can any body pin point the problem....In state s6 I am reading out the
values from FPGA. State s2 and s3 are not defined.
P_IO_FFS : process(
CLK_2X, LOCKED
)
begin
if RISING_EDGE(CLK_2X) then
if LOCKED = '1' then
-- Outputs
-- LED_V3 <= LED_V3_int;
STAT_V3 <= STAT_V3_int;
-- Inputs
SR_ADDR_IO_int <= SR_ADDR_IO;
SR_DATA_IO_int <= SR_DATA_IO;
SR_IRD_int <= SR_IRD;
SR_IWR_int <= SR_IWR;
SR_IVCS_V3_int <= SR_IVCS_V3;
end if;
end if;
end process P_IO_FFS;
Process (CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
SR_DATA_IO_int <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
state_signal <= '0';
if SR_ADDR_IO_int = "000000" then
channelbit1 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000001" then
channelbit2 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000010" then
channelbit3 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000011" then
channelbit4 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int <= "000100" then
channelbit5 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000101" then
channelbit6 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000110" then
channelbit7 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000111" then
channelbit8 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001000" then
channelbit9 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001001" then
channelbit10 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001010" then
channelbit11 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001011" then
channelbit12 <= SR_DATA_IO_int(2 downto 0) ;
state_signal <= '1';
end if;
end if;
end if;
end if;
end process ;
process3 : process (CLK_2X,state)
begin
if RISING_EDGE(CLK_2X) then
case state is
when s1 =>
-- if RISING_EDGE(CLK_2X) then
paritycheck <= '0';
if state_signal = '1' then
k <= 0;
state <= s4;
end if;
-- end if;
when s4 =>
-- if RISING_EDGE(CLK_2X) then
k <= k + 1;
state <= s5;
-- end if;
when s5 =>
-- if RISING_EDGE(CLK_2X) then
if remainder = 0 then
k <= 0;
state <= s6 ;
paritycheck <= '1';
eb_bits <= eb_hat_bits;
else
state <= s4 ;
k<= k+1;
end if ;
-- end if;
when s6 =>
-- if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IRD_int = '0' then
if SR_ADDR_IO_int = "001100" then
SR_DATA_IO (11 downto 0)<= eb_bits;
SR_DATA_IO (31 downto 12) <= "00000000000000000000";
state <= s7;
end if;
else
Null;
end if;
else
Null;
end if ;
-- end if;
when s7 =>
-- if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001101" then
state <= s1;
else Null;end if;
else Null; end if;
else Null; end if;
-- end if;
when others =>
Null;
end case;
end if;
end process process3;
-----------------------------------------------------------------------------------
--Parity Check Process
-- Process (clock)
Process (start,CLK_2X)
begin
if CLK_2X'EVENT and CLK_2X = '1' then
if start = '1' then
address <= address + "001";
data <= eb_hat_bits;
a <= '0';
kk <= '0';
-- t<= '0';
s<= '0';
q<= '0';
elsif start = '0' then
t<= '0';
end if;
if address = "001" then
kk<= '1';
end if;
if address = "010" then
a <= '1' ;
address <= "ZZZ";
end if ;
if a = '1' then
s <= '1';
end if;
if s = '1' then
t <= '1';
address <= "000";
end if;
end if;
end process ;
Process (start,address)
begin
if start = '1' then
case address is
when "000" =>
word1 <= rom( conv_integer("000"));
word2 <= rom( conv_integer("001"));
word3 <= rom( conv_integer("010"));
word4 <= rom( conv_integer("011"));
word5 <= rom( conv_integer("100"));
word6 <= rom( conv_integer("101"));
when others =>
Null;
end case;
end if;
end process ;
Process (a)
begin
if a = '1' then
adderrow1 <= add1 + add2+ add3 + add4 + add5 + add6+add7 + add8+
add9 + add10+add11+add12;
adderrow2 <= adder1_2+adder2_2+adder3_2+adder4_2+adder5_2+adder6_2+
adder7_2+adder8_2+adder9_2+adder10_2+adder11_2+adder12_2;
adderrow3 <= adder1_3+adder2_3+adder3_3+adder4_3+adder5_3+adder6_3+
adder7_3+adder8_3+adder9_3+adder10_3+adder11_3+adder12_3;
adderrow4 <= adder1_4+adder2_4+adder3_4+adder4_4+adder5_4+adder6_4+
adder7_4+adder8_4+adder9_4+adder10_4+adder11_4+adder12_4;
adderrow5 <= adder1_5+adder2_5+adder3_5+adder4_5+adder5_5+adder6_5+
adder7_5+adder8_5+adder9_5+adder10_5+adder11_5+adder12_5;
adderrow6 <= adder1_6+adder2_6+adder3_6+adder4_6+adder5_6+adder6_6+
adder7_6+adder8_6+adder9_6+adder10_6+adder11_6+adder12_6;
else
Null;
end if;
end Process ;
Process (s)
begin
if s = '1' then
-- Addition <= adderrow1 + adderrow2 + adderrow3
-- + adderrow4 + adderrow5 + adderrow6 ;
Remainder1 <= adderrow1 rem 2;
Remainder2 <= adderrow2 rem 2;
Remainder3 <= adderrow3 rem 2;
Remainder4 <= adderrow4 rem 2;
Remainder5 <= adderrow5 rem 2;
Remainder6 <= adderrow6 rem 2;
else
Null;
end if ;
end process ;
Process (t)
begin
if t = '1' then
remainder <= Remainder1 + Remainder2 + Remainder3 + Remainder4
+Remainder5 + Remainder6;
elsif t = '0' then
remainder <= 1;
end if ;
end process ;
state_machine : process (k)
begin
--if (CLK_2X'EVENT and CLK_2X = '1') then
case k is
when 1 =>
--Initialization value at check nodes input coming from variable
node 1
v2c1_1 <= channelbit1;
v2c4_1 <= channelbit1;
v2c6_1 <= channelbit1;
received_1<= channelbit1;
--Initialization value at check nodes input coming from variable
node 2
v2c2_2 <= channelbit2;
v2c3_2 <= channelbit2;
v2c4_2 <= channelbit2;
received_2<= channelbit2;
--Initialization value at check nodes input coming from variable
node 3
v2c1_3 <= channelbit3;
v2c2_3 <= channelbit3;
v2c4_3 <= channelbit3;
received_3<= channelbit3;
--Initialization value at check nodes input coming from variable
node 4
v2c2_4 <= channelbit4;
v2c3_4 <= channelbit4;
v2c5_4 <= channelbit4;
received_4<= channelbit4;
--Initialization value at check nodes input coming from variable
node 5
v2c2_5 <= channelbit5;
v2c5_5 <= channelbit5;
v2c6_5 <= channelbit5;
received_5<= channelbit5;
--Initialization value at check nodes input coming from variable
node 6
v2c1_6 <= channelbit6;
v2c3_6 <= channelbit6;
v2c6_6 <= channelbit6;
received_6<= channelbit6;
--Initialization value at check nodes input coming from variable
node 7
v2c1_7 <= channelbit7;
v2c2_7 <= channelbit7;
v2c5_7 <= channelbit7;
received_7<= channelbit7;
--Initialization value at check nodes input coming from variable
node 8
v2c3_8 <= channelbit8;
v2c4_8 <= channelbit8;
v2c6_8 <= channelbit8;
received_8<= channelbit8;
--Initialization value at check nodes input coming from variable
node 9
v2c1_9 <= channelbit9;
v2c3_9 <= channelbit9;
v2c4_9 <= channelbit9;
received_9<= channelbit9;
--Initialization value at check nodes input coming from variable
node 10
v2c3_10 <= channelbit10;
v2c5_10 <= channelbit10;
v2c6_10 <= channelbit10;
received_10<=channelbit10;
--Initialization value at check nodes input coming from variable
node 11
v2c4_11 <= channelbit11;
v2c5_11 <= channelbit11;
v2c6_11 <= channelbit11;
received_11<= channelbit11;
--Initialization value at check nodes input coming from variable
node 12
v2c1_12 <= channelbit12;
v2c2_12 <= channelbit12;
v2c5_12 <= channelbit12;
received_12<= channelbit12;
when 7|13|19|25| =>
--Incoming messages to check node 1
-- Or outgoing messages from varaible nodes to check node 1
v2c1_1 <= v2c11;
v2c1_3 <= v2c31;
v2c1_6 <= v2c61;
v2c1_7 <= v2c71;
v2c1_9 <= v2c91;
v2c1_12 <= v2c121;
--Incoming messages to check node 2
-- Or outgoing messages from varaible nodes to check node 2
v2c2_2 <= v2c22;
v2c2_3 <= v2c32;
v2c2_4 <= v2c42;
v2c2_5 <= v2c52;
v2c2_7 <= v2c72;
v2c2_12 <= v2c122;
--Incoming messages to check node 3
-- Or outgoing messages from varaible nodes to check node 3
v2c3_2 <= v2c23;
v2c3_4 <= v2c43;
v2c3_6 <= v2c63;
v2c3_8 <= v2c83;
v2c3_9 <= v2c93;
v2c3_10 <= v2c103;
--Incoming messages to check node 4
-- Or outgoing messages from varaible nodes to check node 4
v2c4_1 <= v2c14;
v2c4_2 <= v2c24;
v2c4_3 <= v2c34;
v2c4_8 <= v2c84;
v2c4_9 <= v2c94;
v2c4_11 <= v2c114;
--Incoming messages check node 5
-- Or outgoing messages from varaible nodes to check node 5
v2c5_4 <= v2c45;
v2c5_5 <= v2c55;
v2c5_7 <= v2c75;
v2c5_10 <= v2c105;
v2c5_11 <= v2c115;
v2c5_12 <= v2c125;
--Incoming messages to check node 6
-- Or outgoing messages from varaible nodes to check node 6
v2c6_1 <= v2c16;
v2c6_5 <= v2c56;
v2c6_6 <= v2c66;
v2c6_8 <= v2c86;
v2c6_10 <= v2c106;
v2c6_11 <= v2c116;
start <= '0';
when 2|8|14|20|26=>
--Incoming messages to variable node 1
-- Or outgoing messages from check nodes to variable node 1
c2v11 <= c2v1_1;
c2v14 <= c2v4_1;
c2v16 <= c2v6_1;
--Incoming messages to variable node 2
-- Or outgoing messages from check nodes to variable node 2
c2v22 <= c2v2_2;
c2v23 <= c2v3_2;
c2v24 <= c2v4_2;
--Incoming messages to variable node 3
-- Or outgoing messages from check nodes to variable node 3
c2v31 <= c2v1_3;
c2v32 <= c2v2_3;
c2v34 <= c2v4_3;
--Incoming messages to variable node 4
-- Or outgoing messages from check nodes to variable node 4
c2v42 <= c2v2_4;
c2v43 <= c2v3_4;
c2v45 <= c2v5_4;
--Incoming messages to variable node 5
-- Or outgoing messages from check nodes to variable node 5
c2v52 <= c2v2_5;
c2v55 <= c2v5_5;
c2v56 <= c2v6_5;
--Incoming messages to variable node 6
-- Or outgoing messages from check nodes to variable node 6
c2v61 <= c2v1_6;
c2v63 <= c2v3_6;
c2v66 <= c2v6_6;
--Incoming messages to variable node 7
-- Or outgoing messages from check nodes to variable node 7
c2v71 <= c2v1_7;
c2v72 <= c2v2_7;
c2v75 <= c2v5_7;
--Incoming messages to variable node 8
-- Or outgoing messages from check nodes to variable node 8
c2v83 <= c2v3_8;
c2v84 <= c2v4_8;
c2v86 <= c2v6_8;
--Incoming messages to variable node 9
-- Or outgoing messages from check nodes to variable node 9
c2v91 <= c2v1_9;
c2v93 <= c2v3_9;
c2v94 <= c2v4_9;
--Incoming messages to variable node 10
-- Or outgoing messages from check nodes to variable node 10
c2v103 <= c2v3_10;
c2v105 <= c2v5_10;
c2v106 <= c2v6_10;
--Incoming messages to variable node 11
-- Or outgoing messages from check nodes to variable node 11
c2v114 <= c2v4_11;
c2v115 <= c2v5_11;
c2v116 <= c2v6_11;
--Incoming messages to variable node 12
-- Or outgoing messages from check nodes to variable node 12
c2v121 <= c2v1_12;
c2v122 <= c2v2_12;
c2v125 <= c2v5_12;
start <= '1';
when others =>
Null;
end case ;
-- end if ;
end process state_machine;
multiplication: Process (kk )
-- Multiplication Process Long enough not mentioned
Its Isaac after long time,,,,,,,,,,,,,,I am having problem reading out
values from SRAM in FPGA everytime I try to target SRAM I am getting
0. The code is given below . The check node and variable node
component's function is not mentioned here.
Can any body pin point the problem....In state s6 I am reading out the
values from FPGA. State s2 and s3 are not defined.
P_IO_FFS : process(
CLK_2X, LOCKED
)
begin
if RISING_EDGE(CLK_2X) then
if LOCKED = '1' then
-- Outputs
-- LED_V3 <= LED_V3_int;
STAT_V3 <= STAT_V3_int;
-- Inputs
SR_ADDR_IO_int <= SR_ADDR_IO;
SR_DATA_IO_int <= SR_DATA_IO;
SR_IRD_int <= SR_IRD;
SR_IWR_int <= SR_IWR;
SR_IVCS_V3_int <= SR_IVCS_V3;
end if;
end if;
end process P_IO_FFS;
Process (CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
SR_DATA_IO_int <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
state_signal <= '0';
if SR_ADDR_IO_int = "000000" then
channelbit1 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000001" then
channelbit2 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000010" then
channelbit3 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000011" then
channelbit4 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int <= "000100" then
channelbit5 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000101" then
channelbit6 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000110" then
channelbit7 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "000111" then
channelbit8 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001000" then
channelbit9 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001001" then
channelbit10 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001010" then
channelbit11 <= SR_DATA_IO_int(2 downto 0) ;
elsif SR_ADDR_IO_int = "001011" then
channelbit12 <= SR_DATA_IO_int(2 downto 0) ;
state_signal <= '1';
end if;
end if;
end if;
end if;
end process ;
process3 : process (CLK_2X,state)
begin
if RISING_EDGE(CLK_2X) then
case state is
when s1 =>
-- if RISING_EDGE(CLK_2X) then
paritycheck <= '0';
if state_signal = '1' then
k <= 0;
state <= s4;
end if;
-- end if;
when s4 =>
-- if RISING_EDGE(CLK_2X) then
k <= k + 1;
state <= s5;
-- end if;
when s5 =>
-- if RISING_EDGE(CLK_2X) then
if remainder = 0 then
k <= 0;
state <= s6 ;
paritycheck <= '1';
eb_bits <= eb_hat_bits;
else
state <= s4 ;
k<= k+1;
end if ;
-- end if;
when s6 =>
-- if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IRD_int = '0' then
if SR_ADDR_IO_int = "001100" then
SR_DATA_IO (11 downto 0)<= eb_bits;
SR_DATA_IO (31 downto 12) <= "00000000000000000000";
state <= s7;
end if;
else
Null;
end if;
else
Null;
end if ;
-- end if;
when s7 =>
-- if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001101" then
state <= s1;
else Null;end if;
else Null; end if;
else Null; end if;
-- end if;
when others =>
Null;
end case;
end if;
end process process3;
-----------------------------------------------------------------------------------
--Parity Check Process
-- Process (clock)
Process (start,CLK_2X)
begin
if CLK_2X'EVENT and CLK_2X = '1' then
if start = '1' then
address <= address + "001";
data <= eb_hat_bits;
a <= '0';
kk <= '0';
-- t<= '0';
s<= '0';
q<= '0';
elsif start = '0' then
t<= '0';
end if;
if address = "001" then
kk<= '1';
end if;
if address = "010" then
a <= '1' ;
address <= "ZZZ";
end if ;
if a = '1' then
s <= '1';
end if;
if s = '1' then
t <= '1';
address <= "000";
end if;
end if;
end process ;
Process (start,address)
begin
if start = '1' then
case address is
when "000" =>
word1 <= rom( conv_integer("000"));
word2 <= rom( conv_integer("001"));
word3 <= rom( conv_integer("010"));
word4 <= rom( conv_integer("011"));
word5 <= rom( conv_integer("100"));
word6 <= rom( conv_integer("101"));
when others =>
Null;
end case;
end if;
end process ;
Process (a)
begin
if a = '1' then
adderrow1 <= add1 + add2+ add3 + add4 + add5 + add6+add7 + add8+
add9 + add10+add11+add12;
adderrow2 <= adder1_2+adder2_2+adder3_2+adder4_2+adder5_2+adder6_2+
adder7_2+adder8_2+adder9_2+adder10_2+adder11_2+adder12_2;
adderrow3 <= adder1_3+adder2_3+adder3_3+adder4_3+adder5_3+adder6_3+
adder7_3+adder8_3+adder9_3+adder10_3+adder11_3+adder12_3;
adderrow4 <= adder1_4+adder2_4+adder3_4+adder4_4+adder5_4+adder6_4+
adder7_4+adder8_4+adder9_4+adder10_4+adder11_4+adder12_4;
adderrow5 <= adder1_5+adder2_5+adder3_5+adder4_5+adder5_5+adder6_5+
adder7_5+adder8_5+adder9_5+adder10_5+adder11_5+adder12_5;
adderrow6 <= adder1_6+adder2_6+adder3_6+adder4_6+adder5_6+adder6_6+
adder7_6+adder8_6+adder9_6+adder10_6+adder11_6+adder12_6;
else
Null;
end if;
end Process ;
Process (s)
begin
if s = '1' then
-- Addition <= adderrow1 + adderrow2 + adderrow3
-- + adderrow4 + adderrow5 + adderrow6 ;
Remainder1 <= adderrow1 rem 2;
Remainder2 <= adderrow2 rem 2;
Remainder3 <= adderrow3 rem 2;
Remainder4 <= adderrow4 rem 2;
Remainder5 <= adderrow5 rem 2;
Remainder6 <= adderrow6 rem 2;
else
Null;
end if ;
end process ;
Process (t)
begin
if t = '1' then
remainder <= Remainder1 + Remainder2 + Remainder3 + Remainder4
+Remainder5 + Remainder6;
elsif t = '0' then
remainder <= 1;
end if ;
end process ;
state_machine : process (k)
begin
--if (CLK_2X'EVENT and CLK_2X = '1') then
case k is
when 1 =>
--Initialization value at check nodes input coming from variable
node 1
v2c1_1 <= channelbit1;
v2c4_1 <= channelbit1;
v2c6_1 <= channelbit1;
received_1<= channelbit1;
--Initialization value at check nodes input coming from variable
node 2
v2c2_2 <= channelbit2;
v2c3_2 <= channelbit2;
v2c4_2 <= channelbit2;
received_2<= channelbit2;
--Initialization value at check nodes input coming from variable
node 3
v2c1_3 <= channelbit3;
v2c2_3 <= channelbit3;
v2c4_3 <= channelbit3;
received_3<= channelbit3;
--Initialization value at check nodes input coming from variable
node 4
v2c2_4 <= channelbit4;
v2c3_4 <= channelbit4;
v2c5_4 <= channelbit4;
received_4<= channelbit4;
--Initialization value at check nodes input coming from variable
node 5
v2c2_5 <= channelbit5;
v2c5_5 <= channelbit5;
v2c6_5 <= channelbit5;
received_5<= channelbit5;
--Initialization value at check nodes input coming from variable
node 6
v2c1_6 <= channelbit6;
v2c3_6 <= channelbit6;
v2c6_6 <= channelbit6;
received_6<= channelbit6;
--Initialization value at check nodes input coming from variable
node 7
v2c1_7 <= channelbit7;
v2c2_7 <= channelbit7;
v2c5_7 <= channelbit7;
received_7<= channelbit7;
--Initialization value at check nodes input coming from variable
node 8
v2c3_8 <= channelbit8;
v2c4_8 <= channelbit8;
v2c6_8 <= channelbit8;
received_8<= channelbit8;
--Initialization value at check nodes input coming from variable
node 9
v2c1_9 <= channelbit9;
v2c3_9 <= channelbit9;
v2c4_9 <= channelbit9;
received_9<= channelbit9;
--Initialization value at check nodes input coming from variable
node 10
v2c3_10 <= channelbit10;
v2c5_10 <= channelbit10;
v2c6_10 <= channelbit10;
received_10<=channelbit10;
--Initialization value at check nodes input coming from variable
node 11
v2c4_11 <= channelbit11;
v2c5_11 <= channelbit11;
v2c6_11 <= channelbit11;
received_11<= channelbit11;
--Initialization value at check nodes input coming from variable
node 12
v2c1_12 <= channelbit12;
v2c2_12 <= channelbit12;
v2c5_12 <= channelbit12;
received_12<= channelbit12;
when 7|13|19|25| =>
--Incoming messages to check node 1
-- Or outgoing messages from varaible nodes to check node 1
v2c1_1 <= v2c11;
v2c1_3 <= v2c31;
v2c1_6 <= v2c61;
v2c1_7 <= v2c71;
v2c1_9 <= v2c91;
v2c1_12 <= v2c121;
--Incoming messages to check node 2
-- Or outgoing messages from varaible nodes to check node 2
v2c2_2 <= v2c22;
v2c2_3 <= v2c32;
v2c2_4 <= v2c42;
v2c2_5 <= v2c52;
v2c2_7 <= v2c72;
v2c2_12 <= v2c122;
--Incoming messages to check node 3
-- Or outgoing messages from varaible nodes to check node 3
v2c3_2 <= v2c23;
v2c3_4 <= v2c43;
v2c3_6 <= v2c63;
v2c3_8 <= v2c83;
v2c3_9 <= v2c93;
v2c3_10 <= v2c103;
--Incoming messages to check node 4
-- Or outgoing messages from varaible nodes to check node 4
v2c4_1 <= v2c14;
v2c4_2 <= v2c24;
v2c4_3 <= v2c34;
v2c4_8 <= v2c84;
v2c4_9 <= v2c94;
v2c4_11 <= v2c114;
--Incoming messages check node 5
-- Or outgoing messages from varaible nodes to check node 5
v2c5_4 <= v2c45;
v2c5_5 <= v2c55;
v2c5_7 <= v2c75;
v2c5_10 <= v2c105;
v2c5_11 <= v2c115;
v2c5_12 <= v2c125;
--Incoming messages to check node 6
-- Or outgoing messages from varaible nodes to check node 6
v2c6_1 <= v2c16;
v2c6_5 <= v2c56;
v2c6_6 <= v2c66;
v2c6_8 <= v2c86;
v2c6_10 <= v2c106;
v2c6_11 <= v2c116;
start <= '0';
when 2|8|14|20|26=>
--Incoming messages to variable node 1
-- Or outgoing messages from check nodes to variable node 1
c2v11 <= c2v1_1;
c2v14 <= c2v4_1;
c2v16 <= c2v6_1;
--Incoming messages to variable node 2
-- Or outgoing messages from check nodes to variable node 2
c2v22 <= c2v2_2;
c2v23 <= c2v3_2;
c2v24 <= c2v4_2;
--Incoming messages to variable node 3
-- Or outgoing messages from check nodes to variable node 3
c2v31 <= c2v1_3;
c2v32 <= c2v2_3;
c2v34 <= c2v4_3;
--Incoming messages to variable node 4
-- Or outgoing messages from check nodes to variable node 4
c2v42 <= c2v2_4;
c2v43 <= c2v3_4;
c2v45 <= c2v5_4;
--Incoming messages to variable node 5
-- Or outgoing messages from check nodes to variable node 5
c2v52 <= c2v2_5;
c2v55 <= c2v5_5;
c2v56 <= c2v6_5;
--Incoming messages to variable node 6
-- Or outgoing messages from check nodes to variable node 6
c2v61 <= c2v1_6;
c2v63 <= c2v3_6;
c2v66 <= c2v6_6;
--Incoming messages to variable node 7
-- Or outgoing messages from check nodes to variable node 7
c2v71 <= c2v1_7;
c2v72 <= c2v2_7;
c2v75 <= c2v5_7;
--Incoming messages to variable node 8
-- Or outgoing messages from check nodes to variable node 8
c2v83 <= c2v3_8;
c2v84 <= c2v4_8;
c2v86 <= c2v6_8;
--Incoming messages to variable node 9
-- Or outgoing messages from check nodes to variable node 9
c2v91 <= c2v1_9;
c2v93 <= c2v3_9;
c2v94 <= c2v4_9;
--Incoming messages to variable node 10
-- Or outgoing messages from check nodes to variable node 10
c2v103 <= c2v3_10;
c2v105 <= c2v5_10;
c2v106 <= c2v6_10;
--Incoming messages to variable node 11
-- Or outgoing messages from check nodes to variable node 11
c2v114 <= c2v4_11;
c2v115 <= c2v5_11;
c2v116 <= c2v6_11;
--Incoming messages to variable node 12
-- Or outgoing messages from check nodes to variable node 12
c2v121 <= c2v1_12;
c2v122 <= c2v2_12;
c2v125 <= c2v5_12;
start <= '1';
when others =>
Null;
end case ;
-- end if ;
end process state_machine;
multiplication: Process (kk )
-- Multiplication Process Long enough not mentioned